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[/] [pulse_processing_algorithm/] [ddr2_iobs.vhd] - Rev 2
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--****************************************************************************** -- -- Xilinx, Inc. 2002 www.xilinx.com -- -- XAPP 253 - Synthesizable DDR SDRAM Controller -- --******************************************************************************* -- -- File name : controller.vhd -- -- --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -- entity ddr2_iobs is port( clk0 : in std_logic; clk180 : in std_logic; clk90 : in std_logic; ddr_rasb_cntrl : in std_logic; ddr_ODT_cntrl : in std_logic; ddr_casb_cntrl : in std_logic; ddr_web_cntrl : in std_logic; ddr_cke_cntrl : in std_logic; ddr_csb_cntrl : in std_logic; ddr_address_cntrl : in std_logic_vector(12 downto 0); ddr_ba_cntrl : in std_logic_vector(1 downto 0); rst_dqs_div_int : in std_logic; dqs_reset : in std_logic; dqs_enable : in std_logic; ddr_dqs : inout std_logic_vector(1 downto 0); ddr_dq : inout std_logic_vector(15 downto 0); write_data_falling: in std_logic_vector(15 downto 0); write_data_rising : in std_logic_vector(15 downto 0); write_en_val : in std_logic; write_en_val1 : in std_logic; reset90_r : in std_logic; data_mask_f : in std_logic_vector(1 downto 0); data_mask_r : in std_logic_vector(1 downto 0); ddr_ODT0 : out std_logic; ddr_rasb : out std_logic; ddr_casb : out std_logic; ddr_web : out std_logic; ddr_ba : out std_logic_vector(1 downto 0); ddr_address : out std_logic_vector(15 downto 0); ddr_cke : out std_logic; ddr_csb : out std_logic; rst_dqs_div : out std_logic; rst_dqs_div_iob : inout std_logic; -- rst_dqs_div_in : in std_logic;--changed by shyam on 13 march -- rst_dqs_div_out : out std_logic;--changed by shyam on 13 march dqs_int_delay_in0 : out std_logic; dqs_int_delay_in1 : out std_logic; dq_in_rising : out std_logic_vector(15 downto 0); dq_in_falling : out std_logic_vector(15 downto 0); --old dq_in : out std_logic_vector(15 downto 0); ddr_dm : out std_logic_vector(1 downto 0) ); end ddr2_iobs; architecture arc_ddr2_iobs of ddr2_iobs is component controller_ddr2_iobs port( clk0 : in std_logic; clk180 : in std_logic; ddr_rasb_cntrl : in std_logic; ddr_casb_cntrl : in std_logic; ddr_web_cntrl : in std_logic; ddr_cke_cntrl : in std_logic; ddr_ODT_cntrl : in std_logic; ddr_csb_cntrl : in std_logic; ddr_address_cntrl: in std_logic_vector(12 downto 0); ddr_ba_cntrl : in std_logic_vector(1 downto 0); rst_dqs_div_int : in std_logic; ddr_ODT0 : out std_logic; ddr_rasb : out std_logic; ddr_casb : out std_logic; ddr_web : out std_logic; ddr_ba : out std_logic_vector(1 downto 0); ddr_address : out std_logic_vector(15 downto 0); ddr_cke : out std_logic; ddr_csb : out std_logic; rst_dqs_div : out std_logic; -- rst_dqs_div_in : in std_logic; -- rst_dqs_div_out : out std_logic rst_dqs_div_iob : inout std_logic ); end component; COMPONENT datapath_ddr2_iobs PORT( clk : IN std_logic; clk90 : IN std_logic; reset90_r : IN std_logic; dqs_reset : IN std_logic; dqs_enable : IN std_logic; write_data_falling : IN std_logic_vector(15 downto 0); write_data_rising : IN std_logic_vector(15 downto 0); write_en_val : IN std_logic; write_en_val1 : IN std_logic; data_mask_f : IN std_logic_vector(1 downto 0); data_mask_r : IN std_logic_vector(1 downto 0); ddr_dqs : INOUT std_logic_vector(1 downto 0); ddr_dq : INOUT std_logic_vector(15 downto 0); dqs_int_delay_in0 : OUT std_logic; dqs_int_delay_in1 : OUT std_logic; ddr_dq_in_rising : OUT std_logic_vector(15 downto 0); ddr_dq_in_falling : OUT std_logic_vector(15 downto 0); ddr_dm : OUT std_logic_vector(1 downto 0) ); END COMPONENT; begin controller_ddr2_iobs0 : controller_ddr2_iobs port map ( clk0 => clk0, clk180 => clk180, ddr_rasb_cntrl => ddr_rasb_cntrl, ddr_casb_cntrl => ddr_casb_cntrl, ddr_web_cntrl => ddr_web_cntrl, ddr_cke_cntrl => ddr_cke_cntrl, ddr_csb_cntrl => ddr_csb_cntrl, ddr_ODT_cntrl => ddr_ODT_cntrl, ddr_address_cntrl => ddr_address_cntrl(12 downto 0), ddr_ba_cntrl => ddr_ba_cntrl(1 downto 0), rst_dqs_div_int => rst_dqs_div_int, --PL: Hela hola... poortje vergeten !!! ddr_ODT0 => ddr_ODT0, -- DIT ZAT ER DUS NIET IN, WAS DEFAULT '0' ddr_rasb => ddr_rasb, ddr_casb => ddr_casb, ddr_web => ddr_web, ddr_ba => ddr_ba(1 downto 0), ddr_address => ddr_address(15 downto 0), ddr_cke => ddr_cke, ddr_csb => ddr_csb, rst_dqs_div => rst_dqs_div, -- rst_dqs_div_in => rst_dqs_div_in, -- rst_dqs_div_out => rst_dqs_div_out ); rst_dqs_div_iob => rst_dqs_div_iob ); datapath_ddr2_iobs0 : datapath_ddr2_iobs port map ( clk => clk0, clk90 => clk90, reset90_r => reset90_r, dqs_reset => dqs_reset, dqs_enable => dqs_enable, ddr_dqs => ddr_dqs(1 downto 0), ddr_dq => ddr_dq(15 downto 0), write_data_falling => write_data_falling(15 downto 0), write_data_rising => write_data_rising(15 downto 0), write_en_val => write_en_val, write_en_val1 => write_en_val1, data_mask_f => data_mask_f(1 downto 0), data_mask_r => data_mask_r(1 downto 0), dqs_int_delay_in0 => dqs_int_delay_in0, dqs_int_delay_in1 => dqs_int_delay_in1, ddr_dq_in_rising => dq_in_rising(15 downto 0), ddr_dq_in_falling => dq_in_falling(15 downto 0), --old ddr_dq_val => dq_in(15 downto 0), ddr_dm => ddr_dm(1 downto 0) ); end arc_ddr2_iobs;