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[/] [pulse_processing_algorithm/] [ddr_clk_dcm.vhd] - Rev 2
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--****************************************************************************** -- --******************************************************************************* -- -- File name : ddr_clk_dcm.vhd -- --***************************************************************************** library ieee; use ieee.std_logic_1164.all; -- -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -- entity ddr_clk_dcm is port( sys_clk : in std_logic; rst : in std_logic; clk_int : out std_logic; clk180_int : out std_logic; clk90_int : out std_logic; clk270_int : out std_logic; dcm_lock : out std_logic; ddr1_clk : out std_logic; ddr1_clkb : out std_logic; ddr2_clk : out std_logic; ddr2_clkb : out std_logic); end ddr_clk_dcm; architecture arc_ddr_clk_dcm of ddr_clk_dcm is attribute syn_keep : boolean; attribute xc_props : string; component DCM -- pragma translate_off generic ( DLL_FREQUENCY_MODE : string := "LOW"; DUTY_CYCLE_CORRECTION : boolean := TRUE ); -- pragma translate_on port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector(7 downto 0) ); end component; component myBUFG port ( I : in std_logic; O : out std_logic); end component; component FDDRRSE port( Q : out std_logic; C0 : in std_logic; C1 : in std_logic; CE : in std_logic; D0 : in std_logic; D1 : in std_logic; R : in std_logic; S : in std_logic); end component; component OBUF port ( O : out std_logic; I : in std_logic); end component; signal clk0dcm : std_logic; signal clk90dcm : std_logic; signal clk0 : std_logic; signal clk0_buf : std_logic; signal clk90_buf : std_logic; signal vcc : std_logic; signal gnd : std_logic; signal dcm1_lock : std_logic; signal ddr1_clk_q :std_logic; signal ddr1_clkb_q :std_logic; signal ddr2_clk_q :std_logic; signal ddr2_clkb_q :std_logic; signal clk180 :std_logic; --signal clk270 : std_logic; attribute DLL_FREQUENCY_MODE : string; attribute DUTY_CYCLE_CORRECTION : string; attribute CLKIN_DIVIDE_BY_2 : string; attribute DLL_FREQUENCY_MODE of DCM_INST1 : label is "LOW"; attribute DUTY_CYCLE_CORRECTION of DCM_INST1 : label is "TRUE"; --attribute CLKIN_DIVIDE_BY_2 of DCM_100 : label is "TRUE"; ---- ************************************************** ---- iob attributes for instantiated FDDRRSE components ---- ************************************************** --PL: --attribute xc_props of U1: label is "IOB=TRUE"; --attribute xc_props of U2: label is "IOB=TRUE"; --attribute xc_props of U3: label is "IOB=TRUE"; --attribute xc_props of U4: label is "IOB=TRUE"; --:LP --attribute syn_keep of clk0 : signal is true; --attribute syn_keep of clk180 : signal is true; --attribute syn_keep of clk270 : signal is true; begin vcc <= '1'; gnd <= '0'; DCM_INST1 : DCM port map ( CLKIN => sys_clk, CLKFB => clk0_buf, DSSEN => gnd, PSINCDEC => gnd, PSEN => gnd, PSCLK => gnd, RST => RST, CLK0 => clk0dcm, CLK90 => clk90dcm, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm1_lock, PSDONE => open, STATUS => open); BUFG_CLK0 : myBUFG port map ( I => clk0dcm , O => clk0_buf); BUFG_CLK90 : myBUFG port map ( I => clk90dcm, O => clk90_buf); clk_int <= clk0_buf; clk180_int <= not clk0_buf; clk90_int <= clk90_buf; clk270_int <= not clk90_buf; dcm_lock <= dcm1_lock; -- and dcm_100_lock; clk0 <= clk0_buf; clk180 <= not clk0_buf; ---- *********************************************************** ---- Output DDR generation ---- This includes instantiation of the output DDR flip flop ---- for ddr clk's and dimm clk's ---- *********************************************************** U1 : FDDRRSE port map ( Q => ddr1_clk_q , C0 => clk0, C1 => clk180, CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd); U2 : FDDRRSE port map ( Q => ddr1_clkb_q , C0 => clk0, C1 => clk180, CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd); U3 : FDDRRSE port map ( Q => ddr2_clk_q , C0 => clk0, C1 => clk180, CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd); U4 : FDDRRSE port map ( Q => ddr2_clkb_q , C0 => clk0, C1 => clk180, CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd); ---- ****************************************** ---- Ouput BUffers for ddr clk's and dimm clk's ---- ****************************************** r1 : OBUF port map ( I => ddr1_clk_q, O => ddr1_clk); r2 : OBUF port map ( I => ddr1_clkb_q, O => ddr1_clkb); r3 : OBUF port map ( I => ddr2_clk_q, O => ddr2_clk); r4 : OBUF port map ( I => ddr2_clkb_q, O => ddr2_clkb); end arc_ddr_clk_dcm;