Subversion Repositories pulse_processing_algorithm

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--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	event_detector.vhd
-- Description	:	Module detects events on the following conditions:
--						- The system is running								(enable = '1')
--						- eventdetection is not inhibited				(gate_in = '1')
--						- a zero-crossing is detected						(zeroX_in = '1')
--						- the signal integral exceeds the threshold	(integral_in > threshold_in)
--						when these conditions are met, event_detect_out becomes '1' for 1 clk-cycle
--						
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
 
entity event_detector is
	Port (	clk					: in STD_LOGIC;
				enable				: in STD_LOGIC := '1';
				gate_in				: in STD_LOGIC;
				zeroX_in				: in STD_LOGIC;
				threshold_in		: in STD_LOGIC_VECTOR;
				integral_in			: in STD_LOGIC_VECTOR;
				event_detect_out	: out STD_LOGIC
			);
end event_detector;
 
architecture Behavioral of event_detector is
 
	constant	WIDTH			: natural := integral_in'length;
 
	signal clk_S					: std_logic := '0';
	signal enable_S				: std_logic := '0';
	signal zeroX_S					: STD_LOGIC := '0';
	signal gate_S					: STD_LOGIC := '0';
	signal event_detect_S		: STD_LOGIC := '0';
	signal threshold_S			: STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others	=> '0');
	signal integral_S				: STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others	=> '0');
 
begin
 
	clk_S					<=	clk;
	enable_S				<=	enable;
	gate_S				<=	gate_in;
	zeroX_S				<=	zeroX_in;
	threshold_S			<=	threshold_in;
	integral_S			<=	integral_in;
	event_detect_out	<=	event_detect_S;
 
	eventdetect : process(clk_S)	-- introduced to compensate for synchronous resets (1 clock cycle delay)
	begin
		if (clk_S'event and clk_S = '1') then
			if (enable_S = '1') then
				if ((zeroX_S = '1') and (integral_S > threshold_S) and (gate_S = '1') and (event_detect_S = '0')) then
					event_detect_S <= '1';
				else 
					event_detect_S <= '0';
				end if;
			end if;
		end if;
	end process;
 
end Behavioral;