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[/] [pulse_processing_algorithm/] [fifo_0_wr_en.vhd] - Rev 2
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-- fifo_wr_en is derived by ORing - -- "rst_dqs_div" , delayed rst_dqs_div with negedge of the ddr_dqs LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -- ENTITY fifo_0_wr_en IS -- Declarations port ( clk : in std_logic; reset : in std_logic; din : in std_logic; rst_dqs_delay_n : out std_logic; dout : out std_logic ); END fifo_0_wr_en ; -- hds interface_end ARCHITECTURE fifo_0_wr_en OF fifo_0_wr_en IS component FDCE port( Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC ); end component; attribute syn_keep : boolean; -- Using Syn_Keep Derictive signal din_delay : STD_ULOGIC; signal TIE_HIGH : STD_ULOGIC; BEGIN rst_dqs_delay_n <= not din_delay; dout <= din or din_delay; TIE_HIGH <= '1'; delay_ff : FDCE port map ( Q => din_delay, C => clk, CE => TIE_HIGH, CLR => reset, D => din ); END fifo_0_wr_en;