Subversion Repositories pulse_processing_algorithm

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--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	flex_ram 
-- Description	:	Inferred like block-RAM but with configurable implementation style
--	
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
 
entity flex_ram is
	generic (RAM_SIZE_PWR	: natural	:= 1;
				FLEX_RAM_STYLE	: string		:= "distributed");
	Port (clk			: in  STD_LOGIC := '0';
         enable		: in  STD_LOGIC := '1';
         write_ptr	: in  STD_LOGIC_VECTOR;
         read_ptr		: in  STD_LOGIC_VECTOR;
			data_in		: in	STD_LOGIC_VECTOR;
         data_out		: out	STD_LOGIC_VECTOR
			);
end flex_ram;
 
architecture Behavioral of flex_ram is
 
 
	constant	WIDTH					: natural := data_in'length;
	constant	MAX_RAM_ADDRESS	: natural := 2**RAM_SIZE_PWR - 1;
	constant ZERO					: STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
 
	type ram_pipe is array (MAX_RAM_ADDRESS downto 0) of STD_LOGIC_VECTOR(WIDTH - 1 downto 0);
	signal mypipe_S : ram_pipe;
	attribute ram_style       			: string;
	attribute ram_style of mypipe_S	: signal is FLEX_RAM_STYLE;
 
	signal clk_S			: STD_LOGIC;
	signal enable_S		: STD_LOGIC;
	signal write_ptr_S	: STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := (others	=> '0');
	signal read_ptr_S		: STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := (others	=> '0');
	signal data_in_S		: STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others	=> '0');
	signal data_out_S		: STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others	=> '0');
 
begin
 
	clk_S			<= clk;
	enable_S		<=	enable;
	write_ptr_S	<= write_ptr;
	read_ptr_S	<= read_ptr;
	data_in_S	<= data_in;
	data_out		<= data_out_S;
 
	ram_RW : process (clk_S)
	begin
		if (clk_S'event and clk_S = '1') then
			if (enable_S = '1') then
				mypipe_S(conv_integer(write_ptr_S)) <= data_in_S;
				data_out_S <= mypipe_S(conv_integer(read_ptr_S));
			end if;
		end if;
	end process;
 
end Behavioral;