Subversion Repositories pulse_processing_algorithm

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--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
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-- Company:			KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author:			P.J.J. Lemmens
-- Design Name:	Feature Extraction
-- Module Name:	mux_sre.vhd
-- Description:	MUltipleXer/switch with input-Select, Reset & Enable
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity mux_sre is
   Port (rst			: in  STD_LOGIC;
			clk			: in  STD_LOGIC;
			enable		: in  STD_LOGIC;
			selectB		: in  STD_LOGIC;
			a				: in  STD_LOGIC_VECTOR;
			b				: in  STD_LOGIC_VECTOR;
			data_valid	: out	STD_LOGIC;
			q				: out STD_LOGIC_VECTOR
		);
end mux_sre;
 
architecture Behavioral of mux_sre is
 
constant	WIDTH			: natural := a'length;
 
signal rst_S			: std_logic := '1';
signal clk_S			: std_logic;
signal enable_S		: std_logic;
signal selectB_S		: std_logic	:=	'0';
signal data_valid_S	: std_logic := '0';
signal a_S				: STD_LOGIC_VECTOR(a'high downto 0);
signal b_S				: STD_LOGIC_VECTOR(b'high downto 0);
signal q_S				: STD_LOGIC_VECTOR(q'high downto 0) := (others => '0');
 
begin
	rst_S				<= rst;
	clk_S				<= clk;
	enable_S			<= enable;
	selectB_S		<=	selectB;
	data_valid		<=	data_valid_S;
	a_S				<= a;
	b_S				<= b;
	q					<= q_S;
 
	process(clk_S, rst_S, enable_S, selectB_S)
	begin
		if rising_edge(clk_S) then
			if rst_S='1' then
				q_S(WIDTH - 1 downto 0) <= (others => '0');
				data_valid_S	<= '0';
			elsif (enable_S = '1') then 
				if (selectB_S = '0') then
					q_S 				<= a_S;
					data_valid_S	<= '1';
				else
					q_S 				<= b_S;
					data_valid_S	<= '1';
				end if;
			else
				data_valid_S	<= '0';
			end if;
		end if;
	end process;
end Behavioral;