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[/] [pulse_processing_algorithm/] [output_mux.vhd] - Rev 2
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----------------------------------------------------------------------------------------------- -- -- Copyright (C) 2011 Peter Lemmens, PANDA collaboration -- p.j.j.lemmens@rug.nl -- http://www-panda.gsi.de -- -- As a reference, please use: -- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner, -- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter" -- Nuclear Inst. and Methods in Physics Research, A .... -- -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA -- ----------------------------------------------------------------------------------------------- -- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands -- Author : P.J.J. Lemmens -- Design Name : Feature Extraction -- Module Name : flex_ram -- Description : multiplexer that collects a set of information of an event(ie.: the features) -- This data is then combined in a packet of data to be presented as output -- in one block. ----------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity output_mux is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; input_valid : in STD_LOGIC; energy_in : in STD_LOGIC_VECTOR; eventnr_in : in STD_LOGIC_VECTOR; fraction_in : in STD_LOGIC_VECTOR; output_valid : out STD_LOGIC; outdata16 : out STD_LOGIC_VECTOR(15 downto 0) ); end output_mux; architecture Behavioral of output_mux is signal rst_S : std_logic := '1'; signal clk_S : std_logic := '0'; signal input_valid_S : std_logic := '0'; signal state_count_S : natural range 0 to 8 := 0; signal energy_S : std_logic_vector(energy_in'high downto 0) := (others => '0'); signal eventnr_S : std_logic_vector(63 downto 0) := (others => '0'); signal fraction_S : std_logic_vector(15 downto 0) := (others => '0'); signal outdata16_S : std_logic_vector(15 downto 0) := (others => '0'); signal output_valid_S : std_logic := '0'; begin rst_S <= rst; clk_S <= clk; input_valid_S <= input_valid; outdata16 <= outdata16_S; output_valid <= output_valid_S; outmux : process(rst_S, clk_S, input_valid_S)--, energy_in, samplenr_in, fraction_in) begin if (clk_S'event and clk_S= '1') then if (rst_S = '1') then state_count_S <= 0; fraction_S <= (others => '0'); outdata16_S <= x"0000"; output_valid_S <= '0'; else if (input_valid_S = '1') then energy_S <= energy_in; eventnr_S <= eventnr_in; fraction_S(fraction_in'high downto 0) <= fraction_in; fraction_S(fraction_S'high downto fraction_in'high + 1) <= (others => '0'); output_valid_S <= '0'; state_count_S <= 8; end if; case conv_integer(state_count_S) is when 8 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= x"aa"; outdata16_S(15 downto 8) <= x"aa"; state_count_S <= state_count_S - 1; when 7 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= eventnr_S(63 downto 56); outdata16_S(15 downto 8) <= eventnr_S(55 downto 48); state_count_S <= state_count_S - 1; when 6 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= eventnr_S(47 downto 40); outdata16_S(15 downto 8) <= eventnr_S(39 downto 32); state_count_S <= state_count_S - 1; when 5 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= eventnr_S(31 downto 24); outdata16_S(15 downto 8) <= eventnr_S(23 downto 16); state_count_S <= state_count_S - 1; when 4 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= eventnr_S(15 downto 8); outdata16_S(15 downto 8) <= eventnr_S(7 downto 0); state_count_S <= state_count_S - 1; when 3 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= fraction_S(15 downto 8); outdata16_S(15 downto 8) <= fraction_S(7 downto 0); state_count_S <= state_count_S - 1; when 2 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= energy_S(15 downto 8); --energy_S(energy_in'high - 8 downto energy_in'high - 15); outdata16_S(15 downto 8) <= energy_S(7 downto 0); --energy_S(energy_in'high downto energy_in'high - 7); state_count_S <= state_count_S - 1; when 1 => output_valid_S <= '1'; outdata16_S(7 downto 0) <= x"55"; outdata16_S(15 downto 8) <= x"55"; state_count_S <= state_count_S - 1; when others => output_valid_S <= '0'; outdata16_S <= (others => '0'); end case; end if; end if; end process; end Behavioral;