Subversion Repositories pulse_processing_algorithm

-----------------------------------------------------------------------------------------------
--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	progdelay_pipeline.vhd
-- Description	:	programmable delayline / datapipe with a (generic-fixed) maximum size
--						
-----------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity progdelay_pipeline is
	generic (RAM_SIZE_PWR	: natural	:= 1;
				FLEX_RAM_STYLE	: string		:= "distributed");
	Port (clk			: in  STD_LOGIC;
			rst			: in  STD_LOGIC;
			enable		: in  STD_LOGIC;
			program		: in  STD_LOGIC;
			delay_in		: in	STD_LOGIC_VECTOR;
			data_in		: in	STD_LOGIC_VECTOR;
			data_out		: out	STD_LOGIC_VECTOR;
			data_valid	: out	std_logic
		);
end progdelay_pipeline;
 
architecture Behavioral of progdelay_pipeline is
 
--	type prog_state_type is (prog_rst, prog_exec, prog_done);
 
	constant	WIDTH					: natural := data_in'length;
	constant	DELAY_WIDTH			: natural := delay_in'length;
	constant	DEFAULT_DELAY		: natural := 8 - 1;
	constant	MAX_RAM_ADDRESS	: natural := 2**RAM_SIZE_PWR - 1;
 
	component flex_ram
	generic (RAM_SIZE_PWR	: natural	:= 1;
				FLEX_RAM_STYLE	: string		:= "distributed");
		Port (clk			: in  STD_LOGIC := '0';
				enable		: in  STD_LOGIC := '0';
				write_ptr	: in  STD_LOGIC_VECTOR;
				read_ptr		: in  STD_LOGIC_VECTOR;
				data_in		: in	STD_LOGIC_VECTOR;
				data_out		: out	STD_LOGIC_VECTOR
				);
	end component;
 
--	signal prog_state_S	: prog_state_type := prog_rst;
 
	signal clk_S			: STD_LOGIC := '0';
	signal rst_S			: STD_LOGIC := '1';
	signal program_S		: STD_LOGIC := '0';
	signal enable_S		: STD_LOGIC := '0';
	signal data_valid_S	: STD_LOGIC := '0';
	signal delay_S			: STD_LOGIC_VECTOR(delay_in'high downto 0) 	:= conv_std_logic_vector(DEFAULT_DELAY + 1, DELAY_WIDTH);
	signal data_in_S		: STD_LOGIC_VECTOR(WIDTH - 1 downto 0)			:= (others	=> '0');
	signal del_data_S		: STD_LOGIC_VECTOR(WIDTH - 1 downto 0)			:= (others	=> '0');
	signal data_out_S		: STD_LOGIC_VECTOR(WIDTH - 1 downto 0)			:= (others	=> '0');
 
	signal write_ptr_S	: STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := conv_std_logic_vector(DEFAULT_DELAY, RAM_SIZE_PWR);
	signal read_ptr_S		: STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := (others	=> '0');
 
	signal rst_count_S	: STD_LOGIC_VECTOR(RAM_SIZE_PWR downto 0) := conv_std_logic_vector(DEFAULT_DELAY + 1, RAM_SIZE_PWR + 1);
 
begin
	pipe_ram : flex_ram
		generic map(RAM_SIZE_PWR	=> RAM_SIZE_PWR,
						FLEX_RAM_STYLE	=> FLEX_RAM_STYLE)
		Port map(clk			=>	clk_S,
					enable		=> enable_S,
					write_ptr	=> write_ptr_S,
					read_ptr		=> read_ptr_S,
					data_in		=> data_in_S,
					data_out		=> del_data_S
				);
 
 
	clk_S			<= clk;
	rst_S			<=	rst;
	enable_S		<=	enable;
	program_S	<= program;
	delay_S		<= delay_in;
	data_in_S	<= data_in;
	data_out		<= data_out_S;
	data_valid	<=	data_valid_S;
 
------------------------------------------------------
----------------------------------------------------
	rst_fake : process (clk_S)
		begin
		if rising_edge(clk_S) then
			if (rst_S = '1') or (program_S = '1') then
				if (delay_S >= 4) then
					rst_count_S <= conv_std_logic_vector(conv_integer(delay_S - 1), RAM_SIZE_PWR + 1);
				else
					rst_count_S <= conv_std_logic_vector((4), RAM_SIZE_PWR + 1);
				end if;
			else
				if (enable_S = '1' and rst_count_S > 0) then
					rst_count_S		<= rst_count_S - 1;
				end if;
			end if;
		end if;
	end process;
----------------------------------------------------
	ram_reg : process (clk_S)
	begin
		if rising_edge(clk_S) then
			if (rst_S = '1') or (program_S = '1') then
				data_out_S		<= (others => '0');
				data_valid_S	<=	'0';
			else
				if (enable_S = '1') then
					if (rst_count_S > 0) then
						data_out_S		<= (others => '0');
						data_valid_S	<=	'0';
					else
						data_out_S		<= del_data_S;
						data_valid_S	<=	'1';
					end if;
				end if;
			end if;
		end if;
	end process;
 
-----------------------------------------------------
	write_ptr : process(clk_S)
	begin
		if rising_edge(clk_S) then
			if (rst_S = '1') or (program_S = '1') then
				if (delay_S >= 4) then	-- to avoid rst_count laggin on delay_S
					write_ptr_S <= conv_std_logic_vector(conv_integer(delay_S) - 2, RAM_SIZE_PWR); -- hier stond delay_S -2 ?!?!
				else
					write_ptr_S <= conv_std_logic_vector((4 - 2), RAM_SIZE_PWR); -- hier stond 4 -2 ?!?!
				end if;
			else 
				if (enable_S ='1') then
					if (write_ptr_S < MAX_RAM_ADDRESS) then
						write_ptr_S <= write_ptr_S + 1;
					else
						write_ptr_S <= (others => '0');
					end if;
				end if;
			end if;
		end if;
	end process;
 
------------------------------------------------------
	read_ptr : process(clk_S)--, init_S, enable_S)
	begin
		if rising_edge(clk_S) then
			if (rst_S = '1') or (program_S = '1') then
				read_ptr_S <= (others => '0');
			else 
				if (enable_S ='1') then
					if (read_ptr_S < MAX_RAM_ADDRESS) then
						read_ptr_S <= read_ptr_S + 1;
					else
						read_ptr_S <= (others => '0');
					end if;
				end if;
			end if;
		end if;
	end process;
 
end Behavioral;