Subversion Repositories pulse_processing_algorithm

--******************************************************************************
--
--  Xilinx, Inc. 2002                 www.xilinx.com
--
--
--*******************************************************************************
--
--  File name :       s3_dqs_iob.vhd
--
--  Description :     This module instantiates DDR IOB output flip-flops, an 
--                    output buffer with registered tri-state, and an input buffer  
--                    for a single strobe/dqs bit. The DDR IOB output flip-flops 
--                    are used to forward strobe to memory during a write. During
--                    a read, the output of the IBUF is routed to the internal 
--                    delay module, dqs_delay. 
--                    
--  Date - revision : 07/28/2003
--
--
-- 
--*****************************************************************************
 
library ieee;
use ieee.std_logic_1164.all;
--library synplify; 
--use synplify.attributes.all;
 
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
 
entity s3_dqs_iob is
port(
     clk            : in std_logic;
     clk180         : in std_logic;
     ddr_dqs_reset  : in std_logic;
     ddr_dqs_enable : in std_logic;
     ddr_dqs        : inout std_logic;
     dqs            : out std_logic);
--attribute syn_noclockbuf : boolean;     
--attribute syn_noclockbuf of ddr_dqs : signal is true;                    
--attribute syn_noclockbuf of dqs     : signal is true;               
end s3_dqs_iob;
 
 
architecture arc_s3_dqs_iob of s3_dqs_iob is
component FD
port( D : in std_logic;
      Q : out std_logic;
      C : in std_logic);
end component;
 
component FDDRRSE 
port( Q  : out std_logic;
      C0 : in std_logic;
      C1 : in std_logic;
      CE : in std_logic;
      D0 : in std_logic;
      D1 : in std_logic;
      R  : in std_logic;
      S  : in std_logic);
end component;
 
component OBUFT
port(
      I : in std_logic;
      T : in std_logic;
      O : out std_logic);
end component;
 
component IBUF_SSTL2_II
port(
      I : in std_logic;
      O : out std_logic);
end component;
 
signal dqs_q            : std_logic;
signal ddr_dqs_enable1  : std_logic;
signal vcc              : std_logic;
signal gnd              : std_logic;
signal ddr_dqs_enable_b : std_logic;
signal data1            : std_logic;
 
begin
 
--***********************************************************************
--     Output DDR generation
--     This includes instantiation of the output DDR flip flop.
--     Additionally, to keep synthesis tools from register sharing, manually
--     instantiate the output tri-state flip-flop.
--*********************************************************************** 
vcc <= '1';
gnd <= '0';
ddr_dqs_enable_b <= not ddr_dqs_enable;
data1 <= '0' when ddr_dqs_reset = '1' else
         '1';
 
 
 
U1 : FD port map  ( D => ddr_dqs_enable_b,
                    Q => ddr_dqs_enable1,
                    C => clk);
 
U2 : FDDRRSE port map (  Q => dqs_q,
                        C0 => clk180,
                        C1 => clk,
                        CE => vcc,
                        D0 => gnd,
                        D1 => data1,
                         R => gnd,
                         S => gnd);
--***********************************************************************
--    IO buffer for dqs signal. Allows for distribution of dqs
--     to the data (DQ) loads.
--***********************************************************************
U3 : OBUFT  port map ( I => dqs_q, 
                       T => ddr_dqs_enable1 ,
                       O => ddr_dqs);
 
U4 : IBUF_SSTL2_II port map ( I => ddr_dqs,
                              O => dqs);
 
 
end arc_s3_dqs_iob;