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[/] [pulse_processing_algorithm/] [sys_clk_dcm.vhd] - Rev 2
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--****************************************************************************** -- --******************************************************************************* -- -- File name : sys_clk_dcm.vhd -- --***************************************************************************** library ieee; use ieee.std_logic_1164.all; -- -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -- entity sys_clk_dcm is port( sys_clk_in : in std_logic; rst : in std_logic; sys_clk_out : out std_logic; sys_clkfx_out : out std_logic; dcm_sys_clock_locked : out std_logic; sys_clk_div2 : out std_logic); end sys_clk_dcm; architecture arc_sys_clk_dcm of sys_clk_dcm is attribute syn_keep : boolean; attribute xc_props : string; component DCM -- pragma translate_off -- generic ( -- DLL_FREQUENCY_MODE : string := "LOW"; -- DUTY_CYCLE_CORRECTION : boolean := TRUE -- ); generic ( CLKDV_DIVIDE : real := 2.0; -- peter CLKFX_DIVIDE : integer := 1 ; CLKFX_MULTIPLY : integer := 4 ) ; -- Delay configuration DONE until DCM LOCK, TRUE/FALSE -- pragma translate_on port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector(7 downto 0) ); end component; component myBUFG port ( I : in std_logic; O : out std_logic); end component; -- signal VCC : std_logic; signal GND : std_logic; signal sys_clk0 : std_logic; signal sys_clkfx : std_logic; signal sys_bufg_clk0 : std_logic; signal sys_bufg_clkfx : std_logic; attribute CLKFX_DIVIDE : integer; attribute CLKFX_MULTIPLY : integer; attribute CLKFX_MULTIPLY of DCM_INST_FX : label is 10; --11 mod. 26.10.2006 attribute CLKFX_DIVIDE of DCM_INST_FX : label is 10; --attribute DLL_FREQUENCY_MODE : string; --attribute DUTY_CYCLE_CORRECTION : string; --attribute CLKIN_DIVIDE_BY_2 : string; --attribute DLL_FREQUENCY_MODE of DCM_INST1 : label is "LOW"; --attribute DUTY_CYCLE_CORRECTION of DCM_INST1 : label is "TRUE"; --attribute CLKIN_DIVIDE_BY_2 of DCM_100 : label is "TRUE"; begin --vcc <= '1'; gnd <= '0'; DCM_INST_FX : DCM port map ( CLKIN => sys_clk_in, CLKFB => sys_bufg_clk0, DSSEN => gnd, PSINCDEC => gnd, PSEN => gnd, PSCLK => gnd, RST => RST, CLK0 => sys_clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLKDV => sys_clk_div2, -- peter CLKFX => sys_clkfx, CLKFX180 => open, LOCKED => dcm_sys_clock_locked, PSDONE => open, STATUS => open); BUFG_SYS_CLK0 : myBUFG port map ( I => sys_clk0 , O => sys_bufg_clk0); BUFG_SYS_CLKFX : myBUFG port map ( I => sys_clkfx, O => sys_bufg_clkfx); sys_clk_out <= sys_bufg_clk0; sys_clkfx_out <= sys_bufg_clkfx; end arc_sys_clk_dcm;