Subversion Repositories pulse_processing_algorithm

-----------------------------------------------------------------------------------------------
--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--		p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company		:	KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands	
-- Author		:	P.J.J. Lemmens
-- Design Name	:	Feature Extraction
-- Module Name	:	window_diff.vhd
-- Description	:	Somewhat obsolete module;	Originally used to calculate the difference 
--						between two samples at a fixed interval. That is still what it does,
--						only: the interval = 1 (where it used to be set by Generics)
--						Data delays were introduced to overcome event-detection latency
--						
-----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
 
entity window_diff is
	Port (	rst			: in	STD_LOGIC;
				clk			: in	STD_LOGIC;
				enable		: in	STD_LOGIC;
				trigger		: in	STD_LOGIC;
				data_in		: in	STD_LOGIC_VECTOR;
				base_out		: out	STD_LOGIC_VECTOR;
				diff_out		: out	STD_LOGIC_VECTOR
			);
end window_diff;
 
architecture Behavioral of window_diff is
 
	constant	WIDTH				:	natural	:= data_in'length;
 
	signal rst_S				: std_logic := '1';
	signal clk_S				: std_logic := '0';
	signal enable_S			: std_logic := '0';
	signal trigger_S			: std_logic := '0';
	signal data_in_S			: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal del1_data_S		: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal del2_data_S		: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal del3_data_S		: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal del4_data_S		: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal del5_data_S		: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal base_data_S		: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal diff_out_S			: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
	signal base_val_S			: std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
--------------------------------------------------------------------------------------------------
 
begin
 
	trigger_delay_proc : process(rst_S, clk_S, enable_S, data_in_S)
		begin
			if (clk_S'event and clk_S = '1') then
				if (rst_S = '1') then
					del1_data_S	<=	(others	=> '0');
					del2_data_S	<=	(others	=> '0');
					del3_data_S	<=	(others	=> '0');
					del4_data_S	<=	(others	=> '0');
				else
					if (enable_S = '1') then
						del1_data_S	<= data_in_S;
						del2_data_S	<= del1_data_S;
						del3_data_S	<= del2_data_S;
						del4_data_S	<= del3_data_S;
					end if;
				end if;
			end if;
	end process;
 
 
	zerox_win_proc : process(rst_S, clk_S, enable_S, del4_data_S)
		begin
			if (clk_S'event and clk_S = '1') then
				if (rst_S = '1') then
					del5_data_S	<=	(others	=> '0');
				else
					if (enable_S = '1') then
						del5_data_S	<= del4_data_S;
						base_data_S	<= del5_data_S;
					end if;
				end if;
			end if;
	end process;
 
	rst_S			<=	rst;
	clk_S			<=	clk;
	enable_S		<=	enable;
	trigger_S	<=	trigger;
	data_in_S	<=	data_in; 
 
	base_out		<= base_val_S;
	diff_out		<=	diff_out_S;
 
	pipe_proc : process(rst_S, clk_S, enable_S, trigger_S, del5_data_S, base_data_S)
		begin
			if (clk_S'event and clk_S = '1') then
				if (rst_S = '1') then
					diff_out_S	<=	(others	=> '0');
					base_val_S	<=	(others	=> '0');
				else
					if  (enable_S = '1') then
						if (trigger_S = '1') then		-- below was: "del3_data_S - base_data_S".... don't know why
							diff_out_S	<= conv_std_logic_vector(conv_integer(signed(del5_data_S)) - conv_integer(signed(base_data_S)), WIDTH);
							base_val_S	<= base_data_S;
						end if;
					end if;
				end if;
			end if;
	end process;
 
end Behavioral;