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[/] [qaz_libs/] [trunk/] [BFM/] [sim/] [tests/] [tb_4_tile_1_outputs/] [tb_4_tile_1_outputs.sv] - Rev 50
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module tb_top();
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
wire aclk = tb_clk;
wire aresetn = ~tb_rst;
tb_base #( .PERIOD(5_000) ) tb( clk_200mhz, tb_rst );
// --------------------------------------------------------------------
//
import avf_4_tile_1_outputs_class_pkg::*;
avf_4_tile_1_outputs_class a_h;
axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis[TILES](.*);
initial
a_h = new(.avf_axis_in_if(avf_axis), .avf_axis_out_if(avf_axis));
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// --------------------------------------------------------------------
//
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// test
the_test test( tb_clk, tb_rst );
initial
begin
test.run_the_test();
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
$display("^^^---------------------------------");
$stop();
end
endmodule
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