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[/] [qaz_libs/] [trunk/] [BFM/] [src/] [tb/] [tb_base.sv] - Rev 50
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////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2019 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// //////////////////////////////////////////////////////////////////////////moduletb_base#(N = 1,realtime PERIODS[N],realtime ASSERT_TIME = (PERIODS[0] * 5) + (PERIODS[0] / 3))(output bit tb_clk[N],output bit tb_aresetn,output bit tb_reset[N]);timeunit 1ns;timeprecision 100ps;// --------------------------------------------------------------------function void assert_reset(realtime reset_assert=ASSERT_TIME);forkbegintb_aresetn = 0;#reset_assert;tb_aresetn = 1;endjoin_noneendfunction// --------------------------------------------------------------------bit disable_clks[N];generatefor(genvar j = 0; j < N; j++) beginalwaysif(disable_clks[j])tb_clk[j] = 0;else#(PERIODS[j]/2) tb_clk[j] = ~tb_clk[j];endendgenerate// --------------------------------------------------------------------generatefor(genvar j = 0; j < N; j++) beginbit reset = 1;assign tb_reset[j] = reset;always @(posedge tb_clk[j] or negedge tb_aresetn)if(~tb_aresetn)reset = 1;elsereset = 0;endendgenerate// --------------------------------------------------------------------initialassert_reset();// --------------------------------------------------------------------endmodule
