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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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//////////////////////////////////////////////////////////////////////


module
  axis_to_riffa_tx
  #(
    N // RIFFA data bus width in bytes
  )
  (
    axis_if       axis_in,
    riffa_chnl_if chnl_bus,
    input [31:0]  tx_len,
    input [30:0]  tx_off,
    input         tx_ready,
    input         tx_last,
    input         clk,
    input         reset
  );

  // --------------------------------------------------------------------
  //
  localparam RW = (N/4); // width of the RIFFA bus in 32 bit words


  // --------------------------------------------------------------------
  //
  wire acked;
  wire [30:0] tx_index;
  // wire tx_done = (tx_index >= tx_len - RW) & tx_ready;
  wire tx_done = (tx_index >= tx_len - RW);

  riffa_chn_tx #(.N(N))
    riffa_chn_tx_i(.*);


  // --------------------------------------------------------------------
  //
  assign axis_in.tready         = chnl_bus.tx_data_ren & acked;
  assign chnl_bus.tx_clk        = clk;
  assign chnl_bus.tx_reset      = reset;
  assign chnl_bus.tx_last       = tx_last;
  assign chnl_bus.tx_len        = tx_len;
  assign chnl_bus.tx_off        = tx_off;
  assign chnl_bus.tx_data_valid = axis_in.tvalid & acked;
  assign chnl_bus.tx_data       = axis_in.tdata;


// --------------------------------------------------------------------
//
endmodule