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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// This source file is free software; you can redistribute it   ////
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//// Public License as published by the Free Software Foundation; ////
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//////////////////////////////////////////////////////////////////////

module
  riffa_chn_tx
  #(
    N // data bus width in bytes
  )
  (
    riffa_chnl_if chnl_bus,
    input tx_ready,
    input tx_done,
    output acked,
    output reg [30:0] tx_index,
    input tx_last,
    input [31:0] tx_len,
    input [30:0] tx_off,

    input clk,
    input reset
  );

  // --------------------------------------------------------------------
  //
  riffa_chnl_tx_fsm
    riffa_chnl_tx_fsm_i
    (
      .tx(chnl_bus.tx),
      .tx_ack(chnl_bus.tx_ack),
      .*
    );


  // --------------------------------------------------------------------
  //
  always_ff @(posedge clk)
    if(reset | ~chnl_bus.tx | tx_done)
      tx_index = 0;
    else if(chnl_bus.tx_data_valid & chnl_bus.tx_data_ren)
      tx_index <= tx_index + (N/4); // increment by 32 bit words


// --------------------------------------------------------------------
//
endmodule