Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  riffa_register_file
  #(
    A, //  address bus width
    N, //  data bus width in bytes
    MW = 3 //  mux select width
  )
  (
    riffa_chnl_if chnl_in,
    riffa_register_if r_if,
    input clk,  // must be same clock domain as rx_clk & tx_clk
    input reset // must be same clock domain as rx_clk & tx_clk
  );

// --------------------------------------------------------------------
// synthesis translate_off
    initial
      a_data_bus_mod: assert(N % 4 == 0) else $fatal;
// synthesis translate_on
// --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //
  localparam RW = (N/4); // width of the bus in 32 bit words
  localparam MI = 2 ** MW; //  mux inputs
  localparam LB = $clog2(RW);
  localparam UB = LB + MW;


  // --------------------------------------------------------------------
  //
  wire rx_done;
  wire [31:0] rx_index;
  wire rx_last;
  wire [31:0] rx_len;
  wire [30:0] rx_off;
  wire rx_data_ren;
  wire rd_empty;
  wire [(8*N)-1:0] rd_data;
  wire rd_en;

  riffa_chn_rx #(.N(N))
    riffa_chn_rx_i(.*);


  // --------------------------------------------------------------------
  //
  wire register_select [MI-1:0];
  genvar j;

  generate
    for(j = 0; j < MI; j = j + 1)
    begin: decoder_gen
      assign register_select[j] = (rx_index[UB:LB] == j) & (rx_index[31:UB] == 0) ? 1 : 0;

      always_ff @(posedge clk)
        if(reset)
          r_if.register_out[j] <= 0;
        else if(rd_en & register_select[j])
          r_if.register_out[j] <= rd_data;
    end
  endgenerate


  // --------------------------------------------------------------------
  //
  assign chnl_in.rx_data_ren = rx_data_ren;
  assign rd_en = ~rd_empty;


  // --------------------------------------------------------------------
  //
  wire tx_ready = 1;
  wire tx_last = 1;
  wire [31:0] tx_len = RW*MI;
  wire [30:0] tx_off = 0;
  wire [31:0] tx_index;
  wire tx_done = (tx_index >= chnl_in.tx_len - RW);

  riffa_chn_tx #(.N(N))
    riffa_chn_tx_i(.*);


  // --------------------------------------------------------------------
  //
  recursive_mux #(.A(MW), .W(N*8))
    recursive_mux_i
    (
      .select(tx_index[UB:LB]),
      .data_in(r_if.register_in),
      .data_out(chnl_in.tx_data)
    );


  // --------------------------------------------------------------------
  //
  assign chnl_in.rx_clk = clk;
  assign chnl_in.tx_clk = clk;
  assign chnl_in.rx_reset = reset;
  assign chnl_in.tx_reset = reset;
  assign chnl_in.tx_last = 1;
  assign chnl_in.tx_len = RW*MI;
  assign chnl_in.tx_off = 0;
  assign chnl_in.tx_data_valid = 1;


// --------------------------------------------------------------------
//
endmodule