Subversion Repositories qaz_libs

# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AX115S2F45I1SG
set_global_assignment -name TOP_LEVEL_ENTITY a10gx_riffa_top
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

# -------------------------------------------------------------------------- #
set_location_assignment PIN_AU33 -to clk_50

set_location_assignment PIN_BD27 -to cpu_resetn
set_location_assignment PIN_L28 -to user_led_g[0]
set_location_assignment PIN_K26 -to user_led_g[1]
set_location_assignment PIN_K25 -to user_led_g[2]
set_location_assignment PIN_L25 -to user_led_g[3]
set_location_assignment PIN_J24 -to user_led_g[4]
set_location_assignment PIN_A19 -to user_led_g[5]
set_location_assignment PIN_C18 -to user_led_g[6]
set_location_assignment PIN_D18 -to user_led_g[7]
set_location_assignment PIN_L27 -to user_led_r[0]
set_location_assignment PIN_J26 -to user_led_r[1]
set_location_assignment PIN_K24 -to user_led_r[2]
set_location_assignment PIN_L23 -to user_led_r[3]
set_location_assignment PIN_B20 -to user_led_r[4]
set_location_assignment PIN_C19 -to user_led_r[5]
set_location_assignment PIN_D19 -to user_led_r[6]
set_location_assignment PIN_M23 -to user_led_r[7]



set_location_assignment PIN_T12 -to user_pb[0]
set_location_assignment PIN_U12 -to user_pb[1]
set_location_assignment PIN_U11 -to user_pb[2]



# -------------------------------------------------------------------------- #
# PCIe
set_location_assignment PIN_BC30 -to pcie_perstn

set_location_assignment PIN_AT40 -to pcie_rx_p[0]
set_location_assignment PIN_AP40 -to pcie_rx_p[1]
set_location_assignment PIN_AN42 -to pcie_rx_p[2]
set_location_assignment PIN_AM40 -to pcie_rx_p[3]
set_location_assignment PIN_AL42 -to pcie_rx_p[4]
set_location_assignment PIN_AK40 -to pcie_rx_p[5]
set_location_assignment PIN_AJ42 -to pcie_rx_p[6]
set_location_assignment PIN_AH40 -to pcie_rx_p[7]

set_location_assignment PIN_BB44 -to pcie_tx_p[0]
set_location_assignment PIN_BA42 -to pcie_tx_p[1]
set_location_assignment PIN_AY44 -to pcie_tx_p[2]
set_location_assignment PIN_AW42 -to pcie_tx_p[3]
set_location_assignment PIN_AV44 -to pcie_tx_p[4]
set_location_assignment PIN_AU42 -to pcie_tx_p[5]
set_location_assignment PIN_AT44 -to pcie_tx_p[6]
set_location_assignment PIN_AR42 -to pcie_tx_p[7]


set_location_assignment PIN_AL37 -to pcie_edge_refclk_p


# -------------------------------------------------------------------------- #
#Group0
set_location_assignment PIN_B28 -to emif_0_mem_mem_dq[0]
set_location_assignment PIN_A28 -to emif_0_mem_mem_dq[1]
set_location_assignment PIN_A27 -to emif_0_mem_mem_dq[2]
set_location_assignment PIN_B27 -to emif_0_mem_mem_dq[3]
set_location_assignment PIN_D27 -to emif_0_mem_mem_dq[4]
set_location_assignment PIN_E27 -to emif_0_mem_mem_dq[5]
set_location_assignment PIN_D26 -to emif_0_mem_mem_dq[6]
set_location_assignment PIN_D28 -to emif_0_mem_mem_dq[7]

set_location_assignment PIN_B26 -to emif_0_mem_mem_dqs[0]
set_location_assignment PIN_C26 -to emif_0_mem_mem_dqs_n[0]

set_location_assignment PIN_E26 -to emif_0_mem_mem_dbi_n[0]


#Group1
set_location_assignment PIN_G25 -to emif_0_mem_mem_dq[8]
set_location_assignment PIN_H25 -to emif_0_mem_mem_dq[9]
set_location_assignment PIN_G26 -to emif_0_mem_mem_dq[10]
set_location_assignment PIN_H26 -to emif_0_mem_mem_dq[11]
set_location_assignment PIN_G28 -to emif_0_mem_mem_dq[12]
set_location_assignment PIN_F27 -to emif_0_mem_mem_dq[13]
set_location_assignment PIN_K27 -to emif_0_mem_mem_dq[14]
set_location_assignment PIN_F28 -to emif_0_mem_mem_dq[15]

set_location_assignment PIN_H28 -to emif_0_mem_mem_dqs[1]
set_location_assignment PIN_J27 -to emif_0_mem_mem_dqs_n[1]

set_location_assignment PIN_G27 -to emif_0_mem_mem_dbi_n[1]


#Group 2
set_location_assignment PIN_D31 -to emif_0_mem_mem_dq[16]
set_location_assignment PIN_E31 -to emif_0_mem_mem_dq[17]
set_location_assignment PIN_B31 -to emif_0_mem_mem_dq[18]
set_location_assignment PIN_C31 -to emif_0_mem_mem_dq[19]
set_location_assignment PIN_A30 -to emif_0_mem_mem_dq[20]
set_location_assignment PIN_E30 -to emif_0_mem_mem_dq[21]
set_location_assignment PIN_B30 -to emif_0_mem_mem_dq[22]
set_location_assignment PIN_D29 -to emif_0_mem_mem_dq[23]

set_location_assignment PIN_C30 -to emif_0_mem_mem_dqs[2]
set_location_assignment PIN_C29 -to emif_0_mem_mem_dqs_n[2]

set_location_assignment PIN_A29 -to emif_0_mem_mem_dbi_n[2]

#Group 3
set_location_assignment PIN_K30 -to emif_0_mem_mem_dq[24]
set_location_assignment PIN_H30 -to emif_0_mem_mem_dq[25]
set_location_assignment PIN_G30 -to emif_0_mem_mem_dq[26]
set_location_assignment PIN_K31 -to emif_0_mem_mem_dq[27]
set_location_assignment PIN_H29 -to emif_0_mem_mem_dq[28]
set_location_assignment PIN_K29 -to emif_0_mem_mem_dq[29]
set_location_assignment PIN_J29 -to emif_0_mem_mem_dq[30]
set_location_assignment PIN_F29 -to emif_0_mem_mem_dq[31]

set_location_assignment PIN_L30 -to emif_0_mem_mem_dqs[3]
set_location_assignment PIN_L29 -to emif_0_mem_mem_dqs_n[3]

set_location_assignment PIN_F30 -to emif_0_mem_mem_dbi_n[3]

#Group 4
set_location_assignment PIN_AC31 -to emif_0_mem_mem_dq[32]
set_location_assignment PIN_AB31 -to emif_0_mem_mem_dq[33]
set_location_assignment PIN_W31 -to emif_0_mem_mem_dq[34]
set_location_assignment PIN_Y31 -to emif_0_mem_mem_dq[35]
set_location_assignment PIN_AD31 -to emif_0_mem_mem_dq[36]
set_location_assignment PIN_AD32 -to emif_0_mem_mem_dq[37]
set_location_assignment PIN_AD33 -to emif_0_mem_mem_dq[38]
set_location_assignment PIN_AA30 -to emif_0_mem_mem_dq[39]

set_location_assignment PIN_Y32 -to emif_0_mem_mem_dqs[4]
set_location_assignment PIN_AA32 -to emif_0_mem_mem_dqs_n[4]

set_location_assignment PIN_AB32 -to emif_0_mem_mem_dbi_n[4]

#Group 5
set_location_assignment PIN_AE31 -to emif_0_mem_mem_dq[40]
set_location_assignment PIN_AE32 -to emif_0_mem_mem_dq[41]
set_location_assignment PIN_AE30 -to emif_0_mem_mem_dq[42]
set_location_assignment PIN_AF30 -to emif_0_mem_mem_dq[43]
set_location_assignment PIN_AG33 -to emif_0_mem_mem_dq[44]
set_location_assignment PIN_AG32 -to emif_0_mem_mem_dq[45]
set_location_assignment PIN_AH33 -to emif_0_mem_mem_dq[46]
set_location_assignment PIN_AH31 -to emif_0_mem_mem_dq[47]

set_location_assignment PIN_AJ32 -to emif_0_mem_mem_dqs[5]
set_location_assignment PIN_AJ31 -to emif_0_mem_mem_dqs_n[5]

set_location_assignment PIN_AG31 -to emif_0_mem_mem_dbi_n[5]

#Group 6
set_location_assignment PIN_U31 -to emif_0_mem_mem_dq[48]
set_location_assignment PIN_W33 -to emif_0_mem_mem_dq[49]
set_location_assignment PIN_W32 -to emif_0_mem_mem_dq[50]
set_location_assignment PIN_V31 -to emif_0_mem_mem_dq[51]
set_location_assignment PIN_Y34 -to emif_0_mem_mem_dq[52]
set_location_assignment PIN_W35 -to emif_0_mem_mem_dq[53]
set_location_assignment PIN_W34 -to emif_0_mem_mem_dq[54]
set_location_assignment PIN_V34 -to emif_0_mem_mem_dq[55]

set_location_assignment PIN_AA34 -to emif_0_mem_mem_dqs[6]
set_location_assignment PIN_AA33 -to emif_0_mem_mem_dqs_n[6]

set_location_assignment PIN_Y35 -to emif_0_mem_mem_dbi_n[6]

#Group 7
set_location_assignment PIN_AH35 -to emif_0_mem_mem_dq[56]
set_location_assignment PIN_AJ34 -to emif_0_mem_mem_dq[57]
set_location_assignment PIN_AJ33 -to emif_0_mem_mem_dq[58]
set_location_assignment PIN_AH34 -to emif_0_mem_mem_dq[59]
set_location_assignment PIN_AD35 -to emif_0_mem_mem_dq[60]
set_location_assignment PIN_AE34 -to emif_0_mem_mem_dq[61]
set_location_assignment PIN_AC33 -to emif_0_mem_mem_dq[62]
set_location_assignment PIN_AD34 -to emif_0_mem_mem_dq[63]

set_location_assignment PIN_AF33 -to emif_0_mem_mem_dqs[7]
set_location_assignment PIN_AF34 -to emif_0_mem_mem_dqs_n[7]

set_location_assignment PIN_AC34 -to emif_0_mem_mem_dbi_n[7]

#Group 8
set_location_assignment PIN_A33 -to emif_0_mem_mem_dq[64]
set_location_assignment PIN_B32 -to emif_0_mem_mem_dq[65]
set_location_assignment PIN_D32 -to emif_0_mem_mem_dq[66]
set_location_assignment PIN_C33 -to emif_0_mem_mem_dq[67]
set_location_assignment PIN_B33 -to emif_0_mem_mem_dq[68]
set_location_assignment PIN_D34 -to emif_0_mem_mem_dq[69]
set_location_assignment PIN_C35 -to emif_0_mem_mem_dq[70]
set_location_assignment PIN_E34 -to emif_0_mem_mem_dq[71]

set_location_assignment PIN_D33 -to emif_0_mem_mem_dqs[8]
set_location_assignment PIN_C34 -to emif_0_mem_mem_dqs_n[8]

set_location_assignment PIN_A32 -to emif_0_mem_mem_dbi_n[8]

# ###########ADDRESS, CLK, RZQ and REF Clock pins##################
#middel tile RZQ
set_location_assignment PIN_J34 -to emif_0_oct_oct_rzqin
#bottom tile RZQ
#set_location_assignment PIN_AF32 -to oct_oct_rzqin

set_location_assignment PIN_M32 -to emif_0_mem_mem_a[0]
set_location_assignment PIN_L32 -to emif_0_mem_mem_a[1]
set_location_assignment PIN_N34 -to emif_0_mem_mem_a[2]
set_location_assignment PIN_M35 -to emif_0_mem_mem_a[3]
set_location_assignment PIN_L34 -to emif_0_mem_mem_a[4]
set_location_assignment PIN_K34 -to emif_0_mem_mem_a[5]
set_location_assignment PIN_M33 -to emif_0_mem_mem_a[6]
set_location_assignment PIN_L33 -to emif_0_mem_mem_a[7]
set_location_assignment PIN_J33 -to emif_0_mem_mem_a[8]
set_location_assignment PIN_J32 -to emif_0_mem_mem_a[9]
set_location_assignment PIN_H31 -to emif_0_mem_mem_a[10]
set_location_assignment PIN_J31 -to emif_0_mem_mem_a[11]
set_location_assignment PIN_H34 -to emif_0_mem_mem_a[12]
set_location_assignment PIN_H33 -to emif_0_mem_mem_a[13]
set_location_assignment PIN_G32 -to emif_0_mem_mem_a[14]
set_location_assignment PIN_E32 -to emif_0_mem_mem_a[15]
set_location_assignment PIN_F32 -to emif_0_mem_mem_a[16]

set_location_assignment PIN_F33 -to emif_0_mem_mem_ba[0]
set_location_assignment PIN_G35 -to emif_0_mem_mem_ba[1]
set_location_assignment PIN_H35 -to emif_0_mem_mem_bg[0]
#set_location_assignment PIN_T34 -to emif_0_mem_mem_bg[1]

set_location_assignment PIN_R30 -to emif_0_mem_mem_ck[0]
set_location_assignment PIN_R31 -to emif_0_mem_mem_ck_n[0]
set_location_assignment PIN_U33 -to emif_0_mem_mem_cke[0]

set_location_assignment PIN_R34 -to emif_0_mem_mem_cs_n[0]
set_location_assignment PIN_P34 -to emif_0_mem_mem_act_n[0]
set_location_assignment PIN_N33 -to emif_0_mem_mem_odt[0]
set_location_assignment PIN_T35 -to emif_0_mem_mem_reset_n[0]
set_location_assignment PIN_T32 -to emif_0_mem_mem_par[0]

set_location_assignment PIN_E35 -to emif_0_mem_mem_alert_n[0]

set_location_assignment PIN_F35 -to "emif_0_pll_ref_clk_clk(n)"
set_location_assignment PIN_F34 -to emif_0_pll_ref_clk_clk

set_instance_assignment -name IO_STANDARD LVDS -to emif_0_pll_ref_clk_clk
set_instance_assignment -name IO_STANDARD LVDS -to "emif_0_pll_ref_clk_clk(n)"


# -------------------------------------------------------------------------- #
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"



# ##############################################################################
# set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005



# -------------------------------------------------------------------------- #
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:make_pof.tcl"


# -------------------------------------------------------------------------- #


set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_50
set_instance_assignment -name IO_STANDARD "1.8 V" -to cpu_resetn
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_r
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_perstn
set_instance_assignment -name IO_STANDARD CML -to pcie_rx_p
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_rx_p
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_tx_p
set_instance_assignment -name IO_STANDARD HCSL -to pcie_edge_refclk_p
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to pcie_edge_refclk_p
set_global_assignment -name ENABLE_SIGNALTAP ON

# -------------------------------------------------------------------------- #




# -------------------------------------------------------------------------- #





set_global_assignment -name SEARCH_PATH ../../../../riffa_2.2.2/src
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_sys.sv
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_map_fifo.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/one_hot_encoder.sv
set_global_assignment -name VERILOG_FILE ../../../basal/src/PRBS/prbs_23_to_8.v
set_global_assignment -name VERILOG_FILE ../../../basal/src/synchronize/sync_reset.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/recursive_mux.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_upsizer.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_downsizer.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/tiny_sync_fifo.sv
set_global_assignment -name VERILOG_FILE ../../../basal/src/FIFOs/bc_sync_fifo.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/sync_fifo.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_test_patern.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_axis_test_pattern.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_register_slice.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_mux.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_if.sv
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_async_fifo.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_w.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../riffa_2.2.2/src/riffa_pkg.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_if.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_file.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx_fsm.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx_fsm.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_if.sv
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_writer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_monitor_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_channel_gate_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_buffer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_hdr_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_selector.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_shift.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_alignment_pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/translation_altera.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/syncff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_sync_fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/shiftreg.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_requester.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_reader_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/scsdpram.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxr_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxc_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_requester_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_reader.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_channel_gate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_engine_classic.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rotate.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_output.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_input.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/registers.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/register.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/recv_credit_flow_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_2clk_1w_1r.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_1clk_1w_1r.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/pipeline.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/one_hot_mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_to_mask.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_flag_to_one_hot.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/mux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt_controller.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo_packer_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ff.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/engine_layer.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/demux.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/cross_domain_signal.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/counter.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/chnl_tester.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel_128.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/async_fifo_fwft.v
set_global_assignment -name QSYS_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/A10GXGen2x8If128_PCIe.qsys
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/riffa_wrapper_a10gx.v
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_pcie.sv
set_global_assignment -name QSYS_FILE sys_pll.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top