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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  a10gx_riffa
  #(// Number of RIFFA Channels
    C_NUM_CHNL,
    // Number of PCIe Lanes
    C_NUM_LANES,
    // Settings from Quartus IP Library
    C_PCI_DATA_WIDTH,
    C_MAX_PAYLOAD_BYTES,
    C_LOG_NUM_TAGS,
    C_FPGA_ID
  )
  (
    input  [ 7:0]  pcie_rx_p,          //PCML14  //PCIe Receive Data-req's OCT
    output [ 7:0]  pcie_tx_p,          //PCML14  //PCIe Transmit Data
    input          pcie_edge_refclk_p, //HCSL    //PCIe Clock- Terminate on MB
    input          pcie_perstn,        //1.8V    //PCIe Reset
    input          npor,

    riffa_chnl_if chnl_bus[C_NUM_CHNL],

    output chnl_reset,
    output chnl_clk
  );

  // --------------------------------------------------------------------
  import riffa_pkg::*;

  // --------------------------------------------------------------------
  wire [3:0]                  tl_cfg_add;
  wire [31:0]                 tl_cfg_ctl;
  wire [52:0]                 tl_cfg_sts;
  wire [0:0]                  rx_st_sop;
  wire [0:0]                  rx_st_eop;
  wire [0:0]                  rx_st_err;
  wire [0:0]                  rx_st_valid;
  wire [0:0]                  rx_st_empty;
  wire                        rx_st_ready;
  wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
  wire [0:0]                  tx_st_sop;
  wire [0:0]                  tx_st_eop;
  wire [0:0]                  tx_st_err;
  wire [0:0]                  tx_st_valid;
  wire                        tx_st_ready;
  wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
  wire [0:0]                  tx_st_empty;
  wire                        pld_clk;
  wire                        reset_status;
  wire                        app_msi_req;
  wire                        app_msi_ack;
  wire [7:0]                  ko_cpl_spc_header;
  wire [11:0]                 ko_cpl_spc_data;

  a10gx_riffa_pcie #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
    a10gx_riffa_pcie_i(.*);

  // --------------------------------------------------------------------
  wire [C_NUM_CHNL-1:0]                     CHNL_RX_CLK;
  wire [C_NUM_CHNL-1:0]                     CHNL_RX;
  wire [C_NUM_CHNL-1:0]                     CHNL_RX_ACK;
  wire [C_NUM_CHNL-1:0]                     CHNL_RX_LAST;
  wire [(C_NUM_CHNL*32)-1:0]                CHNL_RX_LEN;
  wire [(C_NUM_CHNL*31)-1:0]                CHNL_RX_OFF;
  wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_RX_DATA;
  wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_VALID;
  wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_REN;
  wire [C_NUM_CHNL-1:0]                     CHNL_TX_CLK;
  wire [C_NUM_CHNL-1:0]                     CHNL_TX;
  wire [C_NUM_CHNL-1:0]                     CHNL_TX_ACK;
  wire [C_NUM_CHNL-1:0]                     CHNL_TX_LAST;
  wire [(C_NUM_CHNL*32)-1:0]                CHNL_TX_LEN;
  wire [(C_NUM_CHNL*31)-1:0]                CHNL_TX_OFF;
  wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_TX_DATA;
  wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_VALID;
  wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_REN;

  riffa_chnl_w
    #(
      .C_NUM_CHNL(C_NUM_CHNL),
      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
      .SIG_CHNL_LENGTH_W(SIG_CHNL_LENGTH_W),
      .SIG_CHNL_OFFSET_W(SIG_CHNL_OFFSET_W)
    )
    riffa_chnl_w_i(.*);

  // --------------------------------------------------------------------
  wire rst_out;
  wire riffa_reset;
  wire riffa_clk;
  assign riffa_reset = reset_status;
  assign riffa_clk = pld_clk;
  assign chnl_clk = pld_clk;
  assign chnl_reset = rst_out;

  riffa_wrapper_a10gx
    #(
      .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
      .C_NUM_CHNL                   (C_NUM_CHNL),
      .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
      .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES),
      .C_FPGA_ID                    (C_FPGA_ID)
    )
    riffa
    (
      .RX_ST_READY                   (rx_st_ready),
      .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
      .TX_ST_VALID                   (tx_st_valid[0:0]),
      .TX_ST_EOP                     (tx_st_eop[0:0]),
      .TX_ST_SOP                     (tx_st_sop[0:0]),
      .TX_ST_EMPTY                   (tx_st_empty[0:0]),
      .APP_MSI_REQ                   (app_msi_req),
      .RST_OUT                       (rst_out),
      // Inputs
      .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
      .RX_ST_EOP                     (rx_st_eop[0:0]),
      .RX_ST_SOP                     (rx_st_sop[0:0]),
      .RX_ST_VALID                   (rx_st_valid[0:0]),
      .RX_ST_EMPTY                   (rx_st_empty[0:0]),
      .TX_ST_READY                   (tx_st_ready),
      .TL_CFG_CTL                    (tl_cfg_ctl[SIG_CFG_CTL_W-1:0]),
      .TL_CFG_ADD                    (tl_cfg_add[SIG_CFG_ADD_W-1:0]),
      .TL_CFG_STS                    (tl_cfg_sts[SIG_CFG_STS_W-1:0]),
      .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[SIG_KO_CPLH_W-1:0]),
      .KO_CPL_SPC_DATA               (ko_cpl_spc_data[SIG_KO_CPLD_W-1:0]),
      .APP_MSI_ACK                   (app_msi_ack),
      .PLD_CLK                       (pld_clk),
      .RESET_STATUS                  (reset_status),
      .*
    );

// --------------------------------------------------------------------
endmodule