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[/] [qaz_libs/] [trunk/] [PCIe/] [syn/] [a10gx_riffa/] [a10gx_sys.sv] - Rev 49
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module
a10gx_sys
#(
C_PCI_DATA_WIDTH,
B,
N = (C_PCI_DATA_WIDTH / 8), // width of the bus in bytes
RW = (N/4), // width of the bus in 32 bit words
RC = RW * B // number of available registers
)
(
input clk_50, //1.8V - 50MHz
input cpu_resetn, //1.8V //CPU Reset Pushbutton (TR=0)
output [ 7:0] user_led_g, //1.8V //User LEDs
output [ 7:0] user_led_r, //1.8V //User LEDs
input [ 2:0] user_pb, //1.8V //User Pushbuttons (TR=0)
output npor,
input pcie_perstn, //1.8V //PCIe Reset
output sys_aresetn,
riffa_chnl_if chnl_bus,
riffa_register_if r_if,
input clk,
input reset
);
// --------------------------------------------------------------------
//
wire clk_50mhz;
sys_pll
sys_pll_i
(
.rst(~user_pb[0]),
.refclk(clk_50),
.outclk_0(clk_50mhz),
.locked(sys_aresetn)
);
// --------------------------------------------------------------------
//
riffa_register_file #(.N(N), .B(B))
riffa_register_file_i(.*);
// --------------------------------------------------------------------
//
reg [31:0] fled_counter;
always_ff @(posedge clk_50mhz)
fled_counter <= fled_counter + 1;
// --------------------------------------------------------------------
//
genvar j;
generate
for(j = 0; j < RC; j++)
begin : registers
assign r_if.register_in[j] = r_if.register_out[j];
end
endgenerate
// --------------------------------------------------------------------
//
assign user_led_g[0] = fled_counter[23];
assign user_led_g[7:1] = r_if.register_out[0][7:1];
assign user_led_r = r_if.register_out[0][15:8];
assign npor = pcie_perstn & sys_aresetn;
// --------------------------------------------------------------------
//
endmodule