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[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [src/] [amm_monitor/] [amm_checker.sv] - Rev 47
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module
amm_checker
#(
A = 32, // address bus width
N = 8, // data bus width in bytes
B = 7 // burstcount width
)
(
amm_if amm_s,
amm_if amm_m,
input clk, // amm_monitor_clk.clk
input reset // amm_monitor_clk_reset.reset
);
// --------------------------------------------------------------------
//
localparam A_S = A - $clog2(N) - 1;
// --------------------------------------------------------------------
//
altera_avalon_mm_monitor #(
.AV_ADDRESS_W (A),
.AV_SYMBOL_W (8),
.AV_NUMSYMBOLS (N),
.AV_BURSTCOUNT_W (B),
.USE_READ (1),
.USE_WRITE (1),
.USE_ADDRESS (1),
.USE_BYTE_ENABLE (1),
.USE_BURSTCOUNT (1),
.USE_READ_DATA (1),
.USE_READ_DATA_VALID (1),
.USE_WRITE_DATA (1),
.USE_BEGIN_TRANSFER (0),
.USE_BEGIN_BURST_TRANSFER (0),
.USE_WAIT_REQUEST (1),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.AV_BURST_LINEWRAP (0),
.AV_BURST_BNDR_ONLY (0),
.AV_READ_TIMEOUT (256),
.AV_WRITE_TIMEOUT (256),
.AV_WAITREQUEST_TIMEOUT (1024),
.AV_MAX_PENDING_READS (3),
.AV_MAX_PENDING_WRITES (3),
.AV_FIX_READ_LATENCY (0),
.AV_MAX_READ_LATENCY (100),
.AV_MAX_WAITREQUESTED_READ (100),
.AV_MAX_WAITREQUESTED_WRITE (100),
.MASTER_ADDRESS_TYPE ("SYMBOLS"),
.SLAVE_ADDRESS_TYPE ("WORDS"),
.VHDL_ID (0),
.AV_READRESPONSE_W (8),
.AV_WRITERESPONSE_W (8),
.USE_ARBITERLOCK (0),
.USE_LOCK (0),
.USE_DEBUGACCESS (0),
.USE_TRANSACTIONID (0),
.USE_WRITERESPONSE (0),
.USE_READRESPONSE (0),
.USE_CLKEN (0),
.AV_MAX_CONTINUOUS_READ (5),
.AV_MAX_CONTINUOUS_WRITE (5),
.AV_MAX_CONTINUOUS_WAITREQUEST (5),
.AV_MAX_CONTINUOUS_READDATAVALID (5),
.AV_READ_WAIT_TIME (1),
.AV_WRITE_WAIT_TIME (0),
.REGISTER_WAITREQUEST (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) amm_monitor (
.clk (clk), // clk.clk
.reset (reset), // clk_reset.reset
.avs_waitrequest (amm_s.waitrequest), // s0.waitrequest
.avs_write (amm_s.write), // .write
.avs_read (amm_s.read), // .read
.avs_address (amm_s.address[A_S:0]), // .address
.avs_byteenable (amm_s.byteenable), // .byteenable
.avs_burstcount (amm_s.burstcount), // .burstcount
.avs_readdata (amm_s.readdata), // .readdata
.avs_readdatavalid (amm_s.readdatavalid), // .readdatavalid
.avs_writedata (amm_s.writedata), // .writedata
.avm_waitrequest (amm_m.waitrequest), // m0.waitrequest
.avm_write (amm_m.write), // .write
.avm_read (amm_m.read), // .read
.avm_address (amm_m.address), // .address
.avm_byteenable (amm_m.byteenable), // .byteenable
.avm_burstcount (amm_m.burstcount), // .burstcount
.avm_readdata (amm_m.readdata), // .readdata
.avm_readdatavalid (amm_m.readdatavalid), // .readdatavalid
.avm_writedata (amm_m.writedata), // .writedata
.avs_begintransfer (1'b0), // (terminated)
.avm_begintransfer (), // (terminated)
.avs_beginbursttransfer (1'b0), // (terminated)
.avm_beginbursttransfer (), // (terminated)
.avs_transactionid (8'b00000000), // (terminated)
.avm_transactionid (), // (terminated)
.avs_response (), // (terminated)
.avm_response (2'b00), // (terminated)
.avs_readid (), // (terminated)
.avm_readid (8'b00000000), // (terminated)
.avs_writeresponserequest (1'b0), // (terminated)
.avm_writeresponserequest (), // (terminated)
.avs_writeresponsevalid (), // (terminated)
.avm_writeresponsevalid (1'b0), // (terminated)
.avs_writeid (), // (terminated)
.avm_writeid (8'b00000000), // (terminated)
.avs_arbiterlock (1'b0), // (terminated)
.avm_arbiterlock (), // (terminated)
.avs_lock (1'b0), // (terminated)
.avm_lock (), // (terminated)
.avs_debugaccess (1'b0), // (terminated)
.avm_debugaccess (), // (terminated)
.avs_clken (1'b1), // (terminated)
.avm_clken (), // (terminated)
.avm_readresponse (8'b00000000), // (terminated)
.avs_readresponse (), // (terminated)
.avm_writeresponse (8'b00000000), // (terminated)
.avs_writeresponse () // (terminated)
);
endmodule
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