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[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [src/] [ast_monitor.sv] - Rev 47
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module
ast_monitor
#(
ST_SYMBOL_W,
ST_NUMSYMBOLS,
USE_PACKET,
ST_READY_LATENCY,
USE_CHANNEL = 0,
USE_ERROR = 0,
USE_READY = 1,
USE_VALID = 1,
USE_EMPTY = 1,
ST_ERROR_W = 1,
ST_MAX_PACKET_SIZE = 1,
ST_MAX_CHANNELS = 0,
ST_CHANNEL_W = $clog2(ST_MAX_CHANNELS),
ST_EMPTY_W = (ST_NUMSYMBOLS == 1) ? 1 : $clog2(ST_NUMSYMBOLS)
)
(
ast_if src,
ast_if sink,
input clk,
input reset
);
altera_avalon_st_monitor
#(
.USE_PACKET (USE_PACKET),
.USE_CHANNEL (USE_CHANNEL),
.USE_ERROR (USE_ERROR),
.USE_READY (USE_READY),
.USE_VALID (USE_VALID),
.USE_EMPTY (USE_EMPTY),
.ST_SYMBOL_W (ST_SYMBOL_W),
.ST_NUMSYMBOLS (ST_NUMSYMBOLS),
.ST_CHANNEL_W (ST_CHANNEL_W),
.ST_ERROR_W (ST_ERROR_W),
.ST_EMPTY_W (ST_EMPTY_W),
.ST_READY_LATENCY (ST_READY_LATENCY),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (ST_MAX_CHANNELS),
.ST_MAX_PACKET_SIZE (ST_MAX_PACKET_SIZE),
.VHDL_ID (0)
)
altera_avalon_st_monitor_i
(
.clk (clk), // clk.clk
.reset (reset), // clk_reset.reset
.src_data (src.data), // src.data
.src_valid (src.valid), // .valid
.src_ready (src.ready), // .ready
.src_startofpacket (src.startofpacket), // .startofpacket
.src_endofpacket (src.endofpacket), // .endofpacket
.src_empty (src.empty), // .empty
.src_channel (src.channel), // .channel
.src_error (src.error), // .error
.sink_data (sink.data), // sink.data
.sink_valid (sink.valid), // .valid
.sink_ready (sink.ready), // .ready
.sink_startofpacket (sink.startofpacket), // .startofpacket
.sink_endofpacket (sink.endofpacket), // .endofpacket
.sink_empty (sink.empty), // .empty
.sink_channel (sink.channel), // .channel
.sink_error (sink.error) // .error
);
// --------------------------------------------------------------------
//
endmodule
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