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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
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//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//////////////////////////////////////////////////////////////////////


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_100mhz;
  wire tb_clk = clk_100mhz;
  wire tb_rst;
  wire aclk = tb_clk;
  wire aresetn = ~tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);


  // --------------------------------------------------------------------
  //
  localparam A = 32;
  localparam N = 8;


  // --------------------------------------------------------------------
  //
  axi4_if #(.A(A), .N(N))
    axi4_s(.*);
    
  axi4_if #(.A(A), .N(N))
    axi4_m(.*);
    

  // --------------------------------------------------------------------
  //
  axi4_register_slice #(.A(A), .N(N))
    dut(.*);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //
  axi4_checker #(.A(A), .N(N))
    axi4_s_check(.axi4_in(axi4_s));

  axi4_checker #(.A(A), .N(N))
    axi4_m_check(.axi4_in(axi4_m));


  // --------------------------------------------------------------------
  //
  import axi4_simple_agent_pkg::*;


  // --------------------------------------------------------------------
  //
  axi4_master_bfm_if #(.A(A), .N(N))
    tb_axi4_m(.axi4_s(axi4_s), .*);

  axi4_slave_bfm_if #(.A(A), .N(N))
    tb_axi4_s(.axi4_m(axi4_m), .*);


  // --------------------------------------------------------------------
  //
  axi4_simple_agent_class bfm;

  initial
    bfm = new(tb_axi4_m, tb_axi4_s);


  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //  debug wires


  // --------------------------------------------------------------------
  // test
  the_test test( tb_clk, tb_rst );

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule