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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
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//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
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//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
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//////////////////////////////////////////////////////////////////////


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_200mhz;
  wire tb_clk   = clk_200mhz;
  wire tb_rst;

  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);


  // --------------------------------------------------------------------
  //
  wire tb_rst_s;
  wire aclk     = tb_clk;
  wire aresetn  = ~tb_rst_s;

  sync_reset
    sync_reset_i(aclk, tb_rst, tb_rst_s);


  // --------------------------------------------------------------------
  //
  import tb_axis_upsizer_class_pkg::*;


  // --------------------------------------------------------------------
  //
  axis_if #(.N(AVF_N), .U(AVF_U)) axis_in(.*);
  axis_if #(.N(AVF_N * S), .U(AVF_U * S)) axis_out(.*);


  // --------------------------------------------------------------------
  //
  axis_upsizer
    #(
      .N(AVF_N),          // data bus width in bytes
      .I(1),              // TID width
      .D(1),              // TDEST width
      .U(AVF_U),          // TUSER width
      .S(S),              // tdata size multiplier
      .USE_TSTRB(0),      //  set to 1 to enable, 0 to disable
      .USE_TKEEP(0),      //  set to 1 to enable, 0 to disable
      .BYTES_PER_TUSER(0) //  bytes per tuser bit. Set to 0 for transfer based.
    )
    dut(.*);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //
  axis_checker #(.N(AVF_N * S), .I(1), .D(1), .U(AVF_U))
    axis_checker_i(.*);


  // --------------------------------------------------------------------
  //
  axis_if #(.N(AVF_N * S), .U(AVF_U)) avf_axis_in_if(.*);

  assign axis_out.tready = avf_axis_in_if.tready;
  assign avf_axis_in_if.tvalid  = axis_out.tvalid;
  assign avf_axis_in_if.tdata = axis_out.tdata;
  assign avf_axis_in_if.tuser = {axis_out.tuser[(AVF_U*S)-1], axis_out.tuser[1:0]};
  assign avf_axis_in_if.tlast = axis_out.tlast;


  // --------------------------------------------------------------------
  //
  tb_axis_upsizer_class a_h;

  initial
    a_h = new(.avf_axis_in_if(avf_axis_in_if), .avf_axis_out_if(axis_in));


  // --------------------------------------------------------------------
  //

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //  debug wires


  // --------------------------------------------------------------------
  // test
  the_test test( tb_clk, tb_rst );

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule