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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_catenate.sv] - Rev 37
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////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2017 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// //////////////////////////////////////////////////////////////////////////moduleaxis_catenate#(N, // data bus width in bytesI = 1, // TID widthD = 1, // TDEST widthU = 1, // TUSER widthU_IS_EOP = -1)(axis_if axis_in [1:0],axis_if axis_out,input aclk,input aresetn);// --------------------------------------------------------------------//wire select;wire axis_eop;defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are needed these for recursive modules?defparam axis_eop_mux_i.MA = 1;axis_eop_mux// axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1))axis_eop_mux_i(.axis_in(axis_in), .*);// --------------------------------------------------------------------// state machine binary definitionsenum reg [1:0]{HEAD = 2'b01,TAIL = 2'b10} state, next_state;// --------------------------------------------------------------------// state machine flopalways_ff @(posedge aclk)if(~aresetn)state <= HEAD;elsestate <= next_state;// --------------------------------------------------------------------// state machinealways_combcase(state)HEAD: if(axis_eop)next_state <= TAIL;elsenext_state <= HEAD;TAIL: if(axis_eop)next_state <= HEAD;elsenext_state <= TAIL;default: next_state <= HEAD;endcase// --------------------------------------------------------------------//axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus[1:0](.*);genvar j;generateif(U_IS_EOP > -1)begin: u_is_eop_genfor(j = 0; j < U; j++)begin: for_tuser_genif(j == U_IS_EOP)begin: choped_tuser_genassign axis_bus[0].tuser[j] = 0;endelsebegin: tuser_genassign axis_bus[0].tuser[j] = axis_in[0].tuser[j];endendendelseif(U_IS_EOP > -1)begin: tlast_genassign axis_bus[0].tlast = axis_in[0].tlast;endelsebegin: choped_tlast_genassign axis_bus[0].tlast = 0;endendgenerate// --------------------------------------------------------------------//assign axis_in[0].tready = axis_bus[0].tready;assign axis_bus[0].tvalid = axis_in[0].tvalid;assign axis_bus[0].tdata = axis_in[0].tdata;assign axis_bus[0].tstrb = axis_in[0].tstrb;assign axis_bus[0].tkeep = axis_in[0].tkeep;assign axis_bus[0].tid = axis_in[0].tid;assign axis_bus[0].tdest = axis_in[0].tdest;// --------------------------------------------------------------------//axis_aliasaxis_alias_i(axis_in[1], axis_bus[1]);// --------------------------------------------------------------------//defparam axis_mux_i.N = N; // why are needed these for recursive modules?defparam axis_mux_i.I = I;defparam axis_mux_i.D = D;defparam axis_mux_i.U = U;axis_mux// axis_mux #(.N(N), .I(I), .D(D), .U(U))axis_mux_i(.axis_in(axis_bus), .*);// --------------------------------------------------------------------//assign select = (state == HEAD) ? 0 : 1;// --------------------------------------------------------------------//endmodule
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