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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Rev 38
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////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2015 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// //////////////////////////////////////////////////////////////////////////moduleaxis_register_slice#(N, // data bus width in bytesI = 1, // TID widthD = 1, // TDEST widthU = 1, // TUSER widthUSE_TSTRB = 0, // set to 1 to enable, 0 to disableUSE_TKEEP = 0 // set to 1 to enable, 0 to disable)(axis_if axis_in,axis_if axis_out,input aclk,input aresetn);// --------------------------------------------------------------------//localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;// --------------------------------------------------------------------//wire wr_full;wire [W-1:0] wr_data;wire wr_en;wire rd_empty;wire [W-1:0] rd_data;wire rd_en;defparam tiny_sync_fifo_i.W=W; // why are these needed for recursive modules?tiny_sync_fifo// tiny_sync_fifo #(W)tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);// --------------------------------------------------------------------//defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?defparam axis_map_fifo_i.I=I;defparam axis_map_fifo_i.D=D;defparam axis_map_fifo_i.U=U;defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;defparam axis_map_fifo_i.W=W;axis_map_fifo// #(// .N(N),// .I(I),// .D(D),// .U(U),// .USE_TSTRB(USE_TSTRB),// .USE_TKEEP(USE_TKEEP),// .W(W)// )axis_map_fifo_i(.*);// --------------------------------------------------------------------//assign axis_in.tready = ~wr_full;assign wr_en = axis_in.tvalid & ~wr_full;assign axis_out.tvalid = ~rd_empty;assign rd_en = axis_out.tready & ~rd_empty;// --------------------------------------------------------------------//endmodule
