OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_switch.sv] - Rev 51

Go to most recent revision | Compare with Previous | Blame | View Log

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


module
  axis_switch
  #(
    N,      // data bus width in bytes
    I = 1,  // TID width
    D = 1,  // TDEST width
    U = 1   // TUSER width
  )
  (
    input   select,
    axis_if axis_in,
    axis_if axis_out[1:0],
    input   aclk,
    input   aresetn
  );

  // --------------------------------------------------------------------
  //
  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_fanout[1:0](.*);


  // --------------------------------------------------------------------
  //
  assign axis_fanout[0].tdata  = axis_in.tdata;
  assign axis_fanout[0].tstrb  = axis_in.tstrb;
  assign axis_fanout[0].tkeep  = axis_in.tkeep;
  assign axis_fanout[0].tlast  = axis_in.tlast;
  assign axis_fanout[0].tid    = axis_in.tid;
  assign axis_fanout[0].tdest  = axis_in.tdest;
  assign axis_fanout[0].tuser  = axis_in.tuser;


  // --------------------------------------------------------------------
  //
  assign axis_fanout[1].tdata  = axis_in.tdata;
  assign axis_fanout[1].tstrb  = axis_in.tstrb;
  assign axis_fanout[1].tkeep  = axis_in.tkeep;
  assign axis_fanout[1].tlast  = axis_in.tlast;
  assign axis_fanout[1].tid    = axis_in.tid;
  assign axis_fanout[1].tdest  = axis_in.tdest;
  assign axis_fanout[1].tuser  = axis_in.tuser;


  // --------------------------------------------------------------------
  //
  assign axis_in.tready = select ? axis_fanout[1].tready : axis_fanout[0].tready;


  // --------------------------------------------------------------------
  //
  assign axis_fanout[0].tvalid = axis_in.tvalid & (select == 0);
  assign axis_fanout[1].tvalid = axis_in.tvalid & (select == 1);


  // --------------------------------------------------------------------
  //
  defparam axis_register_slice_lo.N = N; // why are these needed for recursive modules?
  defparam axis_register_slice_lo.I = I;
  defparam axis_register_slice_lo.D = D;
  defparam axis_register_slice_lo.U = U;
  defparam axis_register_slice_lo.USE_TSTRB = 0;
  defparam axis_register_slice_lo.USE_TKEEP = 0;
  axis_register_slice
    // #(
      // .N(N),
      // .I(I),
      // .D(D),
      // .U(U),
      // .USE_TSTRB(0),
      // .USE_TKEEP(0)
    // )
    axis_register_slice_lo
    (
      .axis_in(axis_fanout[0]),
      .axis_out(axis_out[0]),
      .*
    );


  // --------------------------------------------------------------------
  //
  // why does questasim need these for recursive modules?
  defparam axis_register_slice_hi.N = N;
  defparam axis_register_slice_hi.I = I;
  defparam axis_register_slice_hi.D = D;
  defparam axis_register_slice_hi.U = U;
  defparam axis_register_slice_hi.USE_TSTRB = 0;
  defparam axis_register_slice_hi.USE_TKEEP = 0;
  axis_register_slice
    // #(
      // .N(N),
      // .I(I),
      // .D(D),
      // .U(U),
      // .USE_TSTRB(0),
      // .USE_TKEEP(0)
    // )
    axis_register_slice_hi
    (
      .axis_in(axis_fanout[1]),
      .axis_out(axis_out[1]),
      .*
    );


// --------------------------------------------------------------------
//
endmodule

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.