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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_switch_allocator.sv] - Rev 36
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////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2017 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// //////////////////////////////////////////////////////////////////////////moduleaxis_switch_allocator#(N, // data bus width in bytesI = 1, // TID widthD = 1, // TDEST widthU = 1, // TUSER widthU_IS_EOP = -1, // set to -1 for tlast, else set to index of tuserSA, // select widthSD = 2 ** SA)(axis_if axis_in,axis_if axis_out[SD-1:0],input aclk,input aresetn);// --------------------------------------------------------------------//wire eop_in;axis_eop_set #(U_IS_EOP)axis_eop_set_i(.axis_in(axis_in),.tready(axis_switch_in.tready),.tvalid(axis_in.tvalid),.axis_eop(eop_in),.*);// --------------------------------------------------------------------//wire eop_out_mux;reg [SA-1:0] select;axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(SA))axis_eop_mux_i(.axis_in(axis_out),.axis_eop(eop_out_mux),.*);// --------------------------------------------------------------------//axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_switch_in(.*);axis_alias #(.CONNECT_TREADY(0), .CONNECT_TVALID(0))axis_alias_i(.axis_out(axis_switch_in), .*);// --------------------------------------------------------------------// state machine binary definitionsenum reg [3:0]{ALLOT = 4'b0001,FLUSH = 4'b0010,SWITCH = 4'b0100,SETTLE = 4'b1000} state, next_state;// --------------------------------------------------------------------// state machine flopalways_ff @(posedge aclk)if(~aresetn)state <= ALLOT;elsestate <= next_state;// --------------------------------------------------------------------// state machinealways_combcase(state)ALLOT: if(eop_in)next_state <= FLUSH;elsenext_state <= ALLOT;FLUSH: if(eop_out_mux)next_state <= SWITCH;elsenext_state <= FLUSH;SWITCH: next_state <= SETTLE;SETTLE: next_state <= ALLOT; // let select propagate to the switchesdefault: next_state <= ALLOT;endcase// --------------------------------------------------------------------//always_ff @(posedge aclk)if(~aresetn)select <= 0;else if(state == SWITCH)select <= select + 1;// --------------------------------------------------------------------//recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA))recursive_axis_switch_i(.axis_in(axis_switch_in), .*);// --------------------------------------------------------------------//assign axis_in.tready = (state == ALLOT) & axis_switch_in.tready;assign axis_switch_in.tvalid = (state == ALLOT) & axis_in.tvalid;// --------------------------------------------------------------------//endmodule
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