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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [analog_devices/] [the_test.sv] - Rev 46
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module
the_test(
input tb_clk,
input tb_rst
);
// --------------------------------------------------------------------
//
import ad_pn_pkg::*;
int data;
// --------------------------------------------------------------------
//
task run_the_test;
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench begun.\n", $time);
$display("^^^---------------------------------");
// --------------------------------------------------------------------
tb_top.tb.timeout_stop(1000ms);
// --------------------------------------------------------------------
wait(~tb_rst);
// --------------------------------------------------------------------
// --------------------------------------------------------------------
tb_top.adc_data = 16'h00ff;
data = pn9({tb_top.adc_data, tb_top.adc_data});
repeat(32) @(posedge tb_clk);
repeat(32)
begin
tb_top.adc_data = data[31:16];
@(posedge tb_clk);
tb_top.adc_data = data[15:0];
data = pn9(data);
@(posedge tb_clk);
end
repeat(8) @(posedge tb_clk);
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
endtask
endmodule
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