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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// This source file is free software; you can redistribute it   ////
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//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//////////////////////////////////////////////////////////////////////


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_200mhz;
  wire tb_clk   = clk_200mhz;
  wire tb_rst;
  wire aclk     = tb_clk;
  wire aresetn  = ~tb_rst;

  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);

  // wire clk_100mhz;
  // tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz);


  // --------------------------------------------------------------------
  //
  localparam W = 8;

  fifo_write_if #(.W(W)) source(clk_200mhz, tb_rst);
  fifo_read_if  #(.W(W)) sink(clk_200mhz, tb_rst);


  // --------------------------------------------------------------------
  //
  tiny_sync_fifo
    dut(.*);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //
  // import fifo_bfm_pkg::*;

  // fifo_bfm_class bfm = new(source, sink);

  // initial
    // bfm.init("", BOTH);


  // --------------------------------------------------------------------
  //
  import fifo_agent_pkg::*;

  fifo_agent_class bfm = new(source, sink);

  initial
  begin
    bfm.init();
    bfm.start_q();
  end



  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //  debug wires


  // --------------------------------------------------------------------
  // test
  the_test test( tb_clk, tb_rst );

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule