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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_fifo/] [fifo_agent.svh] - Rev 51
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
class fifo_agent
extends uvm_agent;
`uvm_component_utils(fifo_agent)
// --------------------------------------------------------------------
virtual fifo_if #(.W(W), .D(D)) vif;
fifo_driver driver_h;
fifo_sequencer sequencer_h;
fifo_monitor monitor_h;
// --------------------------------------------------------------------
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
driver_h = fifo_driver::type_id::create("driver_h", this);
monitor_h = fifo_monitor ::type_id::create("monitor_h", this);
sequencer_h = fifo_sequencer::type_id::create("sequencer_h", this);
endfunction
// --------------------------------------------------------------------
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
driver_h.vif = vif;
monitor_h.vif = vif;
driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction
// --------------------------------------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
// --------------------------------------------------------------------
endclass : fifo_agent
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