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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_one_hot_encoder/] [tb_one_hot_encoder.sv] - Rev 34
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module tb_top();
// --------------------------------------------------------------------
// test bench clock & reset
wire clk_200mhz;
wire tb_clk = clk_200mhz;
wire tb_rst;
tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
// --------------------------------------------------------------------
//
localparam A = 5; // encoder select width
localparam D = 2 ** A;
// --------------------------------------------------------------------
//
reg [A-1:0] select = 0;
wire [D-1:0] encoded;
one_hot_encoder #(A)
dut(.*);
// --------------------------------------------------------------------
// sim models
// | | | | | | | | | | | | | | | | |
// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// --------------------------------------------------------------------
//
// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
// | | | | | | | | | | | | | | | | |
// sim models
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// debug wires
// --------------------------------------------------------------------
// test
initial
begin
// --------------------------------------------------------------------
wait(~tb_rst)
#50ns;
repeat(D + 1)
@(posedge tb_clk)
select++;
// --------------------------------------------------------------------
#50ns;
$display("^^^---------------------------------");
$display("^^^ %16.t | Testbench done.", $time);
$display("^^^---------------------------------");
$display("^^^---------------------------------");
$stop();
end
endmodule