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// --------------------------------------------------------------------
// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
 
module
  bram_tdp
  #(
    parameter W,
    parameter A
  )
  (
    // Port A
    input               a_clk,
    input               a_wr,
    input       [A-1:0] a_addr,
    input       [W-1:0] a_din,
    output  reg [W-1:0] a_dout,
 
    // Port B
    input               b_clk,
    input               b_wr,
    input       [A-1:0] b_addr,
    input       [W-1:0] b_din,
    output  reg [W-1:0] b_dout
  );
 
  // --------------------------------------------------------------------
  // Shared memory
  reg [W-1:0] mem [(2**A)-1:0];
 
 
  // --------------------------------------------------------------------
  // Port A
  always @(posedge a_clk)
  if(a_wr)
  begin
    a_dout      <= a_din;
    mem[a_addr] <= a_din;
  end
  else
    a_dout      <= mem[a_addr];
 
 
  // --------------------------------------------------------------------
  // Port B
  always @(posedge b_clk)
  if(b_wr)
  begin
    b_dout      <= b_din;
    mem[b_addr] <= b_din;
  end
  else
    b_dout      <= mem[b_addr];
 
 
// --------------------------------------------------------------------
//
endmodule