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[/] [qaz_libs/] [trunk/] [basal/] [src/] [misc/] [sr_latch.v] - Rev 47

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module
  sr_latch
  (
    input       set,
    input       reset,
    output reg  out,
 
    input       clock
  );
 
  // --------------------------------------------------------------------
  //
  always @(posedge clock)
    if(reset)
      out <= 0;
    else if(set)
      out <= 1;
 
 
endmodule
 
 

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