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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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module
  sync_reset
  #(
    parameter ASSERT_LENGTH = 8
  )
  (
    input clk_in,
    input async_reset_in,
    output sync_reset_out
  );
 
 
  // --------------------------------------------------------------------
  reg [(ASSERT_LENGTH-1):0] sync_reset_out_r;
  assign    sync_reset_out = sync_reset_out_r[ASSERT_LENGTH-1];
 
  always @(posedge clk_in or posedge async_reset_in)
    if(async_reset_in)
      sync_reset_out_r <= {ASSERT_LENGTH{1'b1}};
    else
      sync_reset_out_r <= {sync_reset_out_r[(ASSERT_LENGTH-2):0], 1'b0};
 
 
endmodule