URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
[/] [qaz_libs/] [trunk/] [camera_link/] [sim/] [src/] [camera_link_clk.v] - Rev 40
Go to most recent revision | Compare with Previous | Blame | View Log
////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2013 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// `timescale 10ps/1ps module camera_link_clk ( input clk_in, output reg [3:0] clk_7x_index, output clk_out_7x, output clock_good, input reset ); // -------------------------------------------------------------------- // clock_mult #( .MULT(7) ) clk_out_7x_i ( .clock_in(clk_in), .clock_out(clk_out_7x), .clock_good(clock_good), .reset(reset) ); // -------------------------------------------------------------------- // wire delayed_clk_in; assign #1 delayed_clk_in = clk_in; wire clk_in_rise = (delayed_clk_in == 1'b0) & (clk_in == 1'b1); always @(posedge clk_out_7x) begin if(clk_in_rise) clk_7x_index <= 5; else if( clk_7x_index >= 6 ) clk_7x_index <= 0; else clk_7x_index <= clk_7x_index + 1; end endmodule
Go to most recent revision | Compare with Previous | Blame | View Log