Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// This source file is free software; you can redistribute it   ////
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//// Public License as published by the Free Software Foundation; ////
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//////////////////////////////////////////////////////////////////////


interface
  tb_channel_link_rx_if
  (
    input [3:0]  p,
    input [3:0]  n,
    input [4:0]  invert_mux,
    input        reset,
    input        clk_p,
    input        clk_n
  );
  
    // --------------------------------------------------------------------
    //
    timeunit 1ps / 1ps;
    time clk_period = 0;
    time clk_7x_period = 0;
    time strobe_delay = 0;
    

    // --------------------------------------------------------------------
    //
    int bit_index;
    logic clk_7x;
    wire tx_clk = invert_mux[4] ? ~clk_p : clk_p;
    
    
    // --------------------------------------------------------------------
    //
    default clocking cb @(posedge tx_clk);
      input p;
      input n;
      input reset;
    endclocking


    // --------------------------------------------------------------------
    //
    localparam B = 7;
    

    // --------------------------------------------------------------------
    //
    task
      generate_clocks
      (
        time clk_7x_period,
        time strobe_delay
      );

        bit_index = 5;
            
        forever
          @(cb)
          begin
          
            #strobe_delay;
            clk_7x <= 1;

            generate_clk_7x_fork : fork
            begin
              repeat((B * 2) - 1)
              begin
                #(clk_7x_period / 2);
                clk_7x <= ~clk_7x;
                
                if(clk_7x == 1)
                  if(bit_index == 6)
                    bit_index = 0;
                  else
                    bit_index++;
                
              end
            end
            join_none

          end

    endtask: generate_clocks
    
    
    // --------------------------------------------------------------------
    //
    logic [6:0] rx_in [4];

    always @(posedge clk_7x)
    begin
      rx_in[3][bit_index] <= invert_mux[3] ? ~p[3] : p[3];
      rx_in[2][bit_index] <= invert_mux[2] ? ~p[2] : p[2];
      rx_in[1][bit_index] <= invert_mux[1] ? ~p[1] : p[1];
      rx_in[0][bit_index] <= invert_mux[0] ? ~p[0] : p[0];
    end
    
    
    // --------------------------------------------------------------------
    //
    logic [27:0] rx_data;

    always @(posedge clk_7x)
      if(bit_index == 6)
      begin
        //        6           5             4           3             2           1             0
        {rx_data[27], rx_data[ 5], rx_data[10], rx_data[11], rx_data[16], rx_data[17], rx_data[23]} <= {invert_mux[3] ? ~p[3] : p[3], rx_in[3][5:0]};
        {rx_data[19], rx_data[20], rx_data[21], rx_data[22], rx_data[24], rx_data[25], rx_data[26]} <= {invert_mux[2] ? ~p[2] : p[2], rx_in[2][5:0]};
        {rx_data[ 8], rx_data[ 9], rx_data[12], rx_data[13], rx_data[14], rx_data[15], rx_data[18]} <= {invert_mux[1] ? ~p[1] : p[1], rx_in[1][5:0]};
        {rx_data[ 0], rx_data[ 1], rx_data[ 2], rx_data[ 3], rx_data[ 4], rx_data[ 6], rx_data[ 7]} <= {invert_mux[0] ? ~p[0] : p[0], rx_in[0][5:0]};
      end
    
    
    // --------------------------------------------------------------------
    //
    wire        dval       = rx_data[26];
    wire        fval       = rx_data[25];
    wire        lval       = rx_data[24];
    wire        spare      = rx_data[23];
    wire [7:0]  port_a_d_g = {rx_data[5],      rx_data[27],    rx_data[6], rx_data[4:0]};
    wire [7:0]  port_b_e_h = {rx_data[11],     rx_data[10],    rx_data[14:12], rx_data[9:7]};
    wire [7:0]  port_c_f   = {rx_data[17:16],  rx_data[22:18], rx_data[15]};
    
  
    // --------------------------------------------------------------------
    //
    task
      init_clocks;

        time clk_rise_t;
        
        @(cb iff ~reset);
        clk_rise_t = $time;

        @(cb iff ~reset);
        clk_period  = $time - clk_rise_t;
        clk_7x_period = clk_period / B;
        strobe_delay = clk_7x_period / 2;

        $display("^^^ %16.t | %m | clk_period     = %t, ", $time, clk_period);
        $display("^^^ %16.t | %m | clk_7x_period  = %t", $time, clk_7x_period);
        $display("^^^ %16.t | %m | strobe_delay   = %t", $time, strobe_delay);

        generate_clocks_fork : fork
          generate_clocks(clk_7x_period, strobe_delay);
        join_none

    endtask: init_clocks


    // --------------------------------------------------------------------
    //
    initial
    begin
    
      wait(~reset);
      #500ns;
      
      init_clocks();
    end
    
    
    // --------------------------------------------------------------------
    //

endinterface