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[/] [qaz_libs/] [trunk/] [camera_link/] [src/] [camera_link_if.sv] - Rev 27
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////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2015 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// //////////////////////////////////////////////////////////////////////////interfacecamera_link_if(input reset,input clk_7x,input clk);wire frame_valid;wire line_valid;wire data_valid;wire [7:0] port_a;wire [7:0] port_b;wire [7:0] port_c;wire [7:0] port_d;wire [7:0] port_e;wire [7:0] port_f;wire [7:0] port_g;wire [7:0] port_h;// --------------------------------------------------------------------//default clocking cb @(posedge clk iff ~reset);input reset;input clk;inout port_a;inout port_b;inout port_c;inout port_d;inout port_e;inout port_f;inout port_g;inout port_h;endclocking// --------------------------------------------------------------------//modportcamera(input reset,input clk_7x,input clk,output data_valid,output frame_valid,output line_valid,output port_a,output port_b,output port_c,output port_d,output port_e,output port_f,output port_g,output port_h,clocking cb);// --------------------------------------------------------------------//modportframe_grabber(input reset,input clk_7x,input clk,input data_valid,input frame_valid,input line_valid,input port_a,input port_b,input port_c,input port_d,input port_e,input port_f,input port_g,input port_h,clocking cb);// --------------------------------------------------------------------//endinterface
