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//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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//// This source file is free software; you can redistribute it   ////
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//////////////////////////////////////////////////////////////////////

module
  avf_kernel_buffer #(N, U, L, AW)
  (
    axis_if axis_in,
    axis_if axis_out,
    input   aclk,
    input   aresetn
  );

  // --------------------------------------------------------------------
  axis_if #(.N(N*L), .U(U)) a_buffer(.*);

  avf_line_buffer #(N, U, L, AW) line_buffer_i(.axis_out(a_buffer), .*);

  // --------------------------------------------------------------------
  localparam W = N * L * 8;
  localparam UB = (W*L) - 1;
  reg [UB:0] column;

  always_ff @(posedge aclk)
    if(a_buffer.tvalid & a_buffer.tready)
      column <= {a_buffer.tdata, column[UB:W]};

  // --------------------------------------------------------------------
  reg [(N*8)-1:0] kernel[L][L];

  generate
    for(genvar j = 0; j < L * L; j++)
    begin: kernel_gen
      assign  kernel[j/L][j%L] = column[j*N*8 +: N*8];
    end
  endgenerate

  // --------------------------------------------------------------------
  wire sof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[0];
  wire sol = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[1];
  wire eol = a_buffer.tvalid & a_buffer.tready & a_buffer.tlast;
  wire eof = a_buffer.tvalid & a_buffer.tready & a_buffer.tuser[2];
  wire primed;

  // --------------------------------------------------------------------
  enum reg [4:0]
    {
      PRIME       = 5'b0_0001,
      SOL         = 5'b0_0010,
      INITIALIZED = 5'b0_0100,
      READY       = 5'b0_1000,
      EOL         = 5'b1_0000
    } state, next_state;

  // --------------------------------------------------------------------
  always_ff @(posedge aclk)
    if(~aresetn)
      state <= PRIME;
    else
      state <= next_state;

  // --------------------------------------------------------------------
  always_comb
    case(state)
      PRIME:        if(primed)
                      next_state = SOL;
                    else
                      next_state = PRIME;

      SOL:          if(axis_out.tready)
                      next_state = READY;
                    else
                      next_state = SOL;

      READY:        if(eol)
                      next_state = EOL;
                    else
                      next_state = READY;

      EOL:          if(axis_out.tready)
                      next_state = PRIME;
                    else
                      next_state = EOL;

      default:      next_state = PRIME;
    endcase

  // --------------------------------------------------------------------
  reg [$clog2(L)-1:0] count;
  assign primed = (count >= L - 1) & a_buffer.tvalid & a_buffer.tready;
  wire changing_state = (next_state != state);
  wire reset_counter = changing_state & (state != EOL);

  always_ff @(posedge aclk)
    if(~aresetn | reset_counter)
      count <= 0;
    else if(a_buffer.tvalid & a_buffer.tready)
      count <= count + 1;

  // --------------------------------------------------------------------
  reg sof_r;
  
  always_ff @(posedge aclk)
    if(~aresetn | (state == READY))
      sof_r <= 0;
    else if(sof)
      sof_r <= 1;
      
  // --------------------------------------------------------------------
  assign a_buffer.tready = (state == PRIME) | axis_out.tready;
  assign axis_out.tvalid = (state != PRIME) & a_buffer.tvalid;
  assign axis_out.tdata = column;
  // assign axis_out.tlast = a_buffer.tlast;
  assign axis_out.tlast = (state == EOL);
  // assign axis_out.tuser = a_buffer.tuser;
  assign axis_out.tuser[0] = (state == SOL) & sof_r;
  assign axis_out.tuser[1] = (state == SOL);
  assign axis_out.tuser[2] = (state == EOL) & eof;

// --------------------------------------------------------------------
endmodule