Subversion Repositories qaz_libs

// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module
  top
  (
    inout [14:0]DDR_Addr,
    inout [2:0]DDR_BankAddr,
    inout DDR_CAS_n,
    inout DDR_Clk,
    inout DDR_Clk_n,
    inout DDR_CKE,
    inout DDR_CS_n,
    inout [3:0]DDR_DM,
    inout [31:0]DDR_DQ,
    inout [3:0]DDR_DQS,
    inout [3:0]DDR_DQS_n,
    inout DDR_ODT,
    inout DDR_RAS_n,
    inout DDR_DRSTB,
    inout DDR_WEB,
    inout DDR_VRN,
    inout DDR_VRP,
    inout [53:0]MIO,
    inout PS_CLK,
    inout PS_PORB,
    inout PS_SRSTB,
 
    input AC_ADR0,  // Audio Codec - Bank 13
    output AC_ADR1,
    inout AC_GPIO0,
    inout AC_GPIO1,
    inout AC_GPIO2,
    inout AC_GPIO3,
    input AC_MCLK,
    input AC_SCK,
    inout AC_SDA,
 
    input GCLK,  // Clock Source - Bank 13
 
    inout JA1,  // JA Pmod - Bank 13
    inout JA10,
    inout JA2,
    inout JA3,
    inout JA4,
    inout JA7,
    inout JA8,
    inout JA9,
 
    inout JB1,  // JB Pmod - Bank 13
    inout JB10,
    inout JB2,
    inout JB3,
    inout JB4,
    inout JB7,
    inout JB8,
    inout JB9,
 
    inout JC1_N,  // JC Pmod - Bank 13
    inout JC1_P,
    inout JC2_N,
    inout JC2_P,
    inout JC3_N,
    inout JC3_P,
    inout JC4_N,
    inout JC4_P,
 
    inout JD1_N,  // JA Pmod - Bank 13
    inout JD1_P,
    inout JD2_N,
    inout JD2_P,
    inout JD3_N,
    inout JD3_P,
    inout JD4_N,
    inout JD4_P,
 
    output OLED_DC, // OLED Display - Bank 13
    output OLED_RES,
    output OLED_SCLK,
    output OLED_SDIN,
    output OLED_VBAT,
    output OLED_VDD,
 
    output HD_CLK, // HDMI Output - Bank 33
    output HD_D0,
    output HD_D1,
    output HD_D10,
    output HD_D11,
    output HD_D12,
    output HD_D13,
    output HD_D14,
    output HS_D15,
    output HD_D2,
    output HD_D3,
    output HD_D4,
    output HD_D5,
    output HD_D6,
    output HD_D7,
    output HD_D8,
    output HD_D9,
    output HD_DE,
    output HD_HSYNC,
    output HD_INT,
    output HD_SCL,
    inout HD_SDA,
    output HD_SPDIF,
    input HD_SPDIFO,
    output HD_VSYNC,
 
    output LD0, // User LEDs - Bank 33
    output        LD1,
    output        LD2,
    output        LD3,
    output        LD4,
    output        LD5,
    output        LD6,
    output        LD7,
 
    output VGA_B1,  // VGA Output - Bank 33
    output VGA_B2,
    output VGA_B3,
    output VGA_B4,
    output VGA_G1,
    output VGA_G2,
    output VGA_G3,
    output VGA_G4,
    output VGA_HS,
    output VGA_R1,
    output VGA_R2,
    output VGA_R3,
    output VGA_R4,
    output VGA_VS,
 
    input BTNC, // User Push Buttons - Bank 34
    input BTND,
    input BTNL,
    input BTNR,
    input BTNU,
 
    input OTG_VBUSOC, // USB OTG Reset - Bank 34
 
    // inout XADC_GIO0,  // XADC GIO - Bank 34
    // inout XADC_GIO1,
    // inout XADC_GIO2,
    // inout XADC_GIO3,
 
    inout PUDC_B, // Miscellaneous - Bank 34
 
    output OTG_RESETN,  // USB OTG Reset - Bank 35
 
    input SW0,  // User DIP Switches - Bank 35
    input SW1,
    input SW2,
    input SW3,
    input SW4,
    input SW5,
    input SW6,
    input SW7,
 
    // input AD0N_R, // XADC AD Channels - Bank 35
    // input AD0P_R,
    // input AD8N_N,
    // input AD8P_R,
 
    output FMC_SCL, // FMC Expansion Connector - Bank 13
    inout FMC_SDA,
 
    inout FMC_PRSNT,  // FMC Expansion Connector - Bank 33
 
    input FMC_CLK0_N, // FMC Expansion Connector - Bank 34
    input FMC_CLK0_P,
    input FMC_LA00_CC_N,
    input FMC_LA00_CC_P,
    input FMC_LA01_CC_N,
    input FMC_LA01_CC_P,
    inout FMC_LA02_N,
    inout FMC_LA02_P,
    inout FMC_LA03_N,
    inout FMC_LA03_P,
    inout FMC_LA04_N,
    inout FMC_LA04_P,
    inout FMC_LA05_N,
    inout FMC_LA05_P,
    inout FMC_LA06_N,
    inout FMC_LA06_P,
    inout FMC_LA07_N,
    inout FMC_LA07_P,
    inout FMC_LA08_N,
    inout FMC_LA08_P,
    inout FMC_LA09_N,
    inout FMC_LA09_P,
    inout FMC_LA10_N,
    inout FMC_LA10_P,
    inout FMC_LA11_N,
    inout FMC_LA11_P,
    inout FMC_LA12_N,
    inout FMC_LA12_P,
    inout FMC_LA13_N,
    inout FMC_LA13_P,
    inout FMC_LA14_N,
    inout FMC_LA14_P,
    inout FMC_LA15_N,
    inout FMC_LA15_P,
    inout FMC_LA16_N,
    inout FMC_LA16_P,
 
    input FMC_CLK1_N, // FMC Expansion Connector - Bank 35
    input FMC_CLK1_P,
    input FMC_LA17_CC_N,
    input FMC_LA17_CC_P,
    input FMC_LA18_CC_N,
    input FMC_LA18_CC_P,
    inout FMC_LA19_N,
    inout FMC_LA19_P,
    inout FMC_LA20_N,
    inout FMC_LA20_P,
    inout FMC_LA21_N,
    inout FMC_LA21_P,
    inout FMC_LA22_N,
    inout FMC_LA22_P,
    inout FMC_LA23_N,
    inout FMC_LA23_P,
    inout FMC_LA24_N,
    inout FMC_LA24_P,
    inout FMC_LA25_N,
    inout FMC_LA25_P,
    inout FMC_LA26_N,
    inout FMC_LA26_P,
    inout FMC_LA27_N,
    inout FMC_LA27_P,
    inout FMC_LA28_N,
    inout FMC_LA28_P,
    inout FMC_LA29_N,
    inout FMC_LA29_P,
    inout FMC_LA30_N,
    inout FMC_LA30_P,
    inout FMC_LA31_N,
    inout FMC_LA31_P,
    inout FMC_LA32_N,
    inout FMC_LA32_P,
    inout FMC_LA33_N,
    inout FMC_LA33_P
  );
 
  // --------------------------------------------------------------------
  //
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_araddr;
  // (* KEEP = "TRUE" *) wire [2:0]  M00_AXI_arprot;
  // (* KEEP = "TRUE" *) wire        M00_AXI_arready;
  // (* KEEP = "TRUE" *) wire        M00_AXI_arvalid;
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_awaddr;
  // (* KEEP = "TRUE" *) wire [2:0]  M00_AXI_awprot;
  // (* KEEP = "TRUE" *) wire        M00_AXI_awready;
  // (* KEEP = "TRUE" *) wire        M00_AXI_awvalid;
  // (* KEEP = "TRUE" *) wire        M00_AXI_bready;
  // (* KEEP = "TRUE" *) wire [1:0]  M00_AXI_bresp;
  // (* KEEP = "TRUE" *) wire        M00_AXI_bvalid;
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_rdata;
  // (* KEEP = "TRUE" *) wire        M00_AXI_rready;
  // (* KEEP = "TRUE" *) wire [1:0]  M00_AXI_rresp;
  // (* KEEP = "TRUE" *) wire        M00_AXI_rvalid;
  // (* KEEP = "TRUE" *) wire [31:0] M00_AXI_wdata;
  // (* KEEP = "TRUE" *) wire        M00_AXI_wready;
  // (* KEEP = "TRUE" *) wire [3:0]  M00_AXI_wstrb;
  // (* KEEP = "TRUE" *) wire        M00_AXI_wvalid;
 
  wire [31:0] M00_AXI_araddr;
  wire [2:0]  M00_AXI_arprot;
  wire        M00_AXI_arready;
  wire        M00_AXI_arvalid;
  wire [31:0] M00_AXI_awaddr;
  wire [2:0]  M00_AXI_awprot;
  wire        M00_AXI_awready;
  wire        M00_AXI_awvalid;
  wire        M00_AXI_bready;
  wire [1:0]  M00_AXI_bresp;
  wire        M00_AXI_bvalid;
  wire [31:0] M00_AXI_rdata;
  wire        M00_AXI_rready;
  wire [1:0]  M00_AXI_rresp;
  wire        M00_AXI_rvalid;
  wire [31:0] M00_AXI_wdata;
  wire        M00_AXI_wready;
  wire [3:0]  M00_AXI_wstrb;
  wire        M00_AXI_wvalid;
 
  wire FCLK_CLK0;
 
  zync
    zync_i
    (
      .DDR_addr(DDR_Addr),
      .DDR_ba(DDR_BankAddr),
      .DDR_cas_n(DDR_CAS_n),
      .DDR_ck_n(DDR_Clk_n),
      .DDR_ck_p(DDR_Clk),
      .DDR_cke(DDR_CKE),
      .DDR_cs_n(DDR_CS_n),
      .DDR_dm(DDR_DM),
      .DDR_dq(DDR_DQ),
      .DDR_dqs_n(DDR_DQS_n),
      .DDR_dqs_p(DDR_DQS),
      .DDR_odt(DDR_ODT),
      .DDR_ras_n(DDR_RAS_n),
      .DDR_reset_n(DDR_DRSTB),
      .DDR_we_n(DDR_WEB),
      .FIXED_IO_ddr_vrn(DDR_VRN),
      .FIXED_IO_ddr_vrp(DDR_VRP),
      .FIXED_IO_mio(MIO),
      .FIXED_IO_ps_clk(PS_CLK),
      .FIXED_IO_ps_porb(PS_PORB),
      .FIXED_IO_ps_srstb(PS_SRSTB),
      .FCLK_CLK0(FCLK_CLK0),
      .M00_AXI_araddr(M00_AXI_araddr),
      .M00_AXI_arprot(M00_AXI_arprot),
      .M00_AXI_arready(M00_AXI_arready),
      .M00_AXI_arvalid(M00_AXI_arvalid),
      .M00_AXI_awaddr(M00_AXI_awaddr),
      .M00_AXI_awprot(M00_AXI_awprot),
      .M00_AXI_awready(M00_AXI_awready),
      .M00_AXI_awvalid(M00_AXI_awvalid),
      .M00_AXI_bready(M00_AXI_bready),
      .M00_AXI_bresp(M00_AXI_bresp),
      .M00_AXI_bvalid(M00_AXI_bvalid),
      .M00_AXI_rdata(M00_AXI_rdata),
      .M00_AXI_rready(M00_AXI_rready),
      .M00_AXI_rresp(M00_AXI_rresp),
      .M00_AXI_rvalid(M00_AXI_rvalid),
      .M00_AXI_wdata(M00_AXI_wdata),
      .M00_AXI_wready(M00_AXI_wready),
      .M00_AXI_wstrb(M00_AXI_wstrb),
      .M00_AXI_wvalid(M00_AXI_wvalid),
      .peripheral_aresetn(peripheral_aresetn)
    );
 
 
  // --------------------------------------------------------------------
  //
  wire [31:0] slv_reg0;
  wire [31:0] slv_reg1;
  wire [31:0] slv_reg2;
  wire [31:0] slv_reg3;
 
  reg_file_v1_0_S00_AXI
  #(
    .C_S_AXI_DATA_WIDTH(32),
    .C_S_AXI_ADDR_WIDTH(4)
  )
  reg_file_v1_0_S00_AXI_inst
  (
    .S_AXI_ACLK(FCLK_CLK0),
    .S_AXI_ARESETN(peripheral_aresetn),
    .S_AXI_AWADDR(M00_AXI_awaddr[3:0]),
    .S_AXI_AWPROT(M00_AXI_awprot),
    .S_AXI_AWVALID(M00_AXI_awvalid),
    .S_AXI_AWREADY(M00_AXI_awready),
    .S_AXI_WDATA(M00_AXI_wdata),
    .S_AXI_WSTRB(M00_AXI_wstrb),
    .S_AXI_WVALID(M00_AXI_wvalid),
    .S_AXI_WREADY(M00_AXI_wready),
    .S_AXI_BRESP(M00_AXI_bresp),
    .S_AXI_BVALID(M00_AXI_bvalid),
    .S_AXI_BREADY(M00_AXI_bready),
    .S_AXI_ARADDR(M00_AXI_araddr[3:0]),
    .S_AXI_ARPROT(M00_AXI_arprot),
    .S_AXI_ARVALID(M00_AXI_arvalid),
    .S_AXI_ARREADY(M00_AXI_arready),
    .S_AXI_RDATA(M00_AXI_rdata),
    .S_AXI_RRESP(M00_AXI_rresp),
    .S_AXI_RVALID(M00_AXI_rvalid),
    .S_AXI_RREADY(M00_AXI_rready),
 
    .slv_reg0(slv_reg0),
    .slv_reg1(slv_reg1),
    .slv_reg2(slv_reg2),
    .slv_reg3(slv_reg3)
 
  );
 
 
  // --------------------------------------------------------------------
  //  outputs
  assign LD0 = slv_reg0[0];
  assign LD1 = slv_reg0[1];
  assign LD2 = slv_reg0[2];
  assign LD3 = slv_reg0[3];
  assign LD4 = slv_reg0[4];
  assign LD5 = slv_reg0[5];
  assign LD6 = slv_reg0[6];
  assign LD7 = slv_reg0[7];
 
  assign AC_ADR1 = 0;
  assign AC_GPIO0 = 'bz;
  assign AC_GPIO1 = 'bz;
  assign AC_GPIO2 = 'bz;
  assign AC_GPIO3 = 'bz;
  assign AC_SDA = 'bz;
 
  assign JA1 = 'bz;  // JA Pmod - Bank 13
  assign JA10 = 'bz;
  assign JA2 = 'bz;
  assign JA3 = 'bz;
  assign JA4 = 'bz;
  assign JA7 = 'bz;
  assign JA8 = 'bz;
  assign JA9 = 'bz;
 
  assign JB1 = 'bz;  // JB Pmod - Bank 13
  assign JB10 = 'bz;
  assign JB2 = 'bz;
  assign JB3 = 'bz;
  assign JB4 = 'bz;
  assign JB7 = 'bz;
  assign JB8 = 'bz;
  assign JB9 = 'bz;
 
  assign JC1_N = 'bz;  // JC Pmod - Bank 13
  assign JC1_P = 'bz;
  assign JC2_N = 'bz;
  assign JC2_P = 'bz;
  assign JC3_N = 'bz;
  assign JC3_P = 'bz;
  assign JC4_N = 'bz;
  assign JC4_P = 'bz;
 
  assign JD1_N = 'bz;  // JA Pmod - Bank 13
  assign JD1_P = 'bz;
  assign JD2_N = 'bz;
  assign JD2_P = 'bz;
  assign JD3_N = 'bz;
  assign JD3_P = 'bz;
  assign JD4_N = 'bz;
  assign JD4_P = 'bz;
 
  assign OLED_DC = 0; // OLED Display - Bank 13
  assign OLED_RES = 0;
  assign OLED_SCLK = 0;
  assign OLED_SDIN = 0;
  assign OLED_VBAT = 0;
  assign OLED_VDD = 0;
 
  assign HD_CLK = 0; // HDMI assign - = 0;Bank 33
  assign HD_D0 = 0;
  assign HD_D1 = 0;
  assign HD_D10 = 0;
  assign HD_D11 = 0;
  assign HD_D12 = 0;
  assign HD_D13 = 0;
  assign HD_D14 = 0;
  assign HS_D15 = 0;
  assign HD_D2 = 0;
  assign HD_D3 = 0;
  assign HD_D4 = 0;
  assign HD_D5 = 0;
  assign HD_D6 = 0;
  assign HD_D7 = 0;
  assign HD_D8 = 0;
  assign HD_D9 = 0;
  assign HD_DE = 0;
  assign HD_HSYNC = 0;
  assign HD_INT = 0;
  assign HD_SCL = 0;
  assign HD_SDA = 'bz;
  assign HD_SPDIF = 0;
  assign HD_VSYNC = 0;
 
  assign VGA_B1 = 0;  // VGA assign - = 0;Bank 33
  assign VGA_B2 = 0;
  assign VGA_B3 = 0;
  assign VGA_B4 = 0;
  assign VGA_G1 = 0;
  assign VGA_G2 = 0;
  assign VGA_G3 = 0;
  assign VGA_G4 = 0;
  assign VGA_HS = 0;
  assign VGA_R1 = 0;
  assign VGA_R2 = 0;
  assign VGA_R3 = 0;
  assign VGA_R4 = 0;
  assign VGA_VS = 0;
 
  // assign XADC_GIO0 = 'bz;  // XADC GIO - Bank 34
  // assign XADC_GIO1 = 'bz;
  // assign XADC_GIO2 = 'bz;
  // assign XADC_GIO3 = 'bz;
 
  assign PUDC_B = 'bz; // Miscellaneous - Bank 34
 
  assign OTG_RESETN = 0;  // USB OTG Reset - Bank 35
 
  assign FMC_SCL = 0; // FMC Expansion Connector - Bank 13
  assign FMC_SDA = 'bz;
 
  assign FMC_PRSNT = 'bz;  // FMC Expansion Connector - Bank 33
 
  assign FMC_LA02_N = 'bz;
  assign FMC_LA02_P = 'bz;
  assign FMC_LA03_N = 'bz;
  assign FMC_LA03_P = 'bz;
  assign FMC_LA04_N = 'bz;
  assign FMC_LA04_P = 'bz;
  assign FMC_LA05_N = 'bz;
  assign FMC_LA05_P = 'bz;
  assign FMC_LA06_N = 'bz;
  assign FMC_LA06_P = 'bz;
  assign FMC_LA07_N = 'bz;
  assign FMC_LA07_P = 'bz;
  assign FMC_LA08_N = 'bz;
  assign FMC_LA08_P = 'bz;
  assign FMC_LA09_N = 'bz;
  assign FMC_LA09_P = 'bz;
  assign FMC_LA10_N = 'bz;
  assign FMC_LA10_P = 'bz;
  assign FMC_LA11_N = 'bz;
  assign FMC_LA11_P = 'bz;
  assign FMC_LA12_N = 'bz;
  assign FMC_LA12_P = 'bz;
  assign FMC_LA13_N = 'bz;
  assign FMC_LA13_P = 'bz;
  assign FMC_LA14_N = 'bz;
  assign FMC_LA14_P = 'bz;
  assign FMC_LA15_N = 'bz;
  assign FMC_LA15_P = 'bz;
  assign FMC_LA16_N = 'bz;
  assign FMC_LA16_P = 'bz;
 
  assign FMC_LA19_N = 'bz;
  assign FMC_LA19_P = 'bz;
  assign FMC_LA20_N = 'bz;
  assign FMC_LA20_P = 'bz;
  assign FMC_LA21_N = 'bz;
  assign FMC_LA21_P = 'bz;
  assign FMC_LA22_N = 'bz;
  assign FMC_LA22_P = 'bz;
  assign FMC_LA23_N = 'bz;
  assign FMC_LA23_P = 'bz;
  assign FMC_LA24_N = 'bz;
  assign FMC_LA24_P = 'bz;
  assign FMC_LA25_N = 'bz;
  assign FMC_LA25_P = 'bz;
  assign FMC_LA26_N = 'bz;
  assign FMC_LA26_P = 'bz;
  assign FMC_LA27_N = 'bz;
  assign FMC_LA27_P = 'bz;
  assign FMC_LA28_N = 'bz;
  assign FMC_LA28_P = 'bz;
  assign FMC_LA29_N = 'bz;
  assign FMC_LA29_P = 'bz;
  assign FMC_LA30_N = 'bz;
  assign FMC_LA30_P = 'bz;
  assign FMC_LA31_N = 'bz;
  assign FMC_LA31_P = 'bz;
  assign FMC_LA32_N = 'bz;
  assign FMC_LA32_P = 'bz;
  assign FMC_LA33_N = 'bz;
  assign FMC_LA33_P = 'bz;
 
 
endmodule