Subversion Repositories qfp32

# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II 32-bit Version 11.1 Build 259 01/25/2012 Service Pack 2 SJ Web Edition
# File: C:\Users\Laama\Documents\Project\B3\Audio.csv
# Generated on: Fri Mar 30 12:36:41 2012

# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.

To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Current Strength,Slew Rate
clock_50,Input,PIN_R8,3,B3_N0,3.3-V LVTTL,,
led[0],Output,PIN_A15,7,B7_N0,3.3-V LVTTL,,
led[1],Output,PIN_A13,7,B7_N0,3.3-V LVTTL,,
led[2],Output,PIN_B13,7,B7_N0,3.3-V LVTTL,,
led[3],Output,PIN_A11,7,B7_N0,3.3-V LVTTL,,
led[4],Output,PIN_D1,1,B1_N0,3.3-V LVTTL,,
led[5],Output,PIN_F3,1,B1_N0,3.3-V LVTTL,,
led[6],Output,PIN_B1,1,B1_N0,3.3-V LVTTL,,
led[7],Output,PIN_L3,2,B2_N0,3.3-V LVTTL,,
key[0],Input,PIN_J15,5,B5_N0,3.3-V LVTTL,,
key[1],Input,PIN_E1,1,B1_N0,3.3-V LVTTL,,
sw[0],Input,PIN_M1,2,B2_N0,3.3-V LVTTL,,
sw[1],Input,PIN_T8,3,B3_N0,3.3-V LVTTL,,
sw[2],Input,PIN_B9,7,B7_N0,3.3-V LVTTL,,
sw[3],Input,PIN_M15,5,B5_N0,3.3-V LVTTL,,
dram_addr[0],Output,PIN_P2,2,B2_N0,3.3-V LVTTL,,
dram_addr[1],Output,PIN_N5,3,B3_N0,3.3-V LVTTL,,
dram_addr[2],Output,PIN_N6,3,B3_N0,3.3-V LVTTL,,
dram_addr[3],Output,PIN_M8,3,B3_N0,3.3-V LVTTL,,
dram_addr[4],Output,PIN_P8,3,B3_N0,3.3-V LVTTL,,
dram_addr[5],Output,PIN_T7,3,B3_N0,3.3-V LVTTL,,
dram_addr[6],Output,PIN_N8,3,B3_N0,3.3-V LVTTL,,
dram_addr[7],Output,PIN_T6,3,B3_N0,3.3-V LVTTL,,
dram_addr[8],Output,PIN_R1,2,B2_N0,3.3-V LVTTL,,
dram_addr[9],Output,PIN_P1,2,B2_N0,3.3-V LVTTL,,
dram_addr[10],Output,PIN_N2,2,B2_N0,3.3-V LVTTL,,
dram_addr[11],Output,PIN_N1,2,B2_N0,3.3-V LVTTL,,
dram_addr[12],Output,PIN_L4,2,B2_N0,3.3-V LVTTL,,
dram_ba[0],Output,PIN_M7,3,B3_N0,3.3-V LVTTL,,
dram_ba[1],Output,PIN_M6,3,B3_N0,3.3-V LVTTL,,
dram_cke,Output,PIN_L7,3,B3_N0,3.3-V LVTTL,,
dram_clk,Output,PIN_R4,3,B3_N0,3.3-V LVTTL,,
dram_cs_n,Output,PIN_P6,3,B3_N0,3.3-V LVTTL,,
dram_dq[0],Bidir,PIN_G2,1,B1_N0,3.3-V LVTTL,,
dram_dq[1],Bidir,PIN_G1,1,B1_N0,3.3-V LVTTL,,
dram_dq[2],Bidir,PIN_L8,3,B3_N0,3.3-V LVTTL,,
dram_dq[3],Bidir,PIN_K5,2,B2_N0,3.3-V LVTTL,,
dram_dq[4],Bidir,PIN_K2,2,B2_N0,3.3-V LVTTL,,
dram_dq[5],Bidir,PIN_J2,2,B2_N0,3.3-V LVTTL,,
dram_dq[6],Bidir,PIN_J1,2,B2_N0,3.3-V LVTTL,,
dram_dq[7],Bidir,PIN_R7,3,B3_N0,3.3-V LVTTL,,
dram_dq[8],Bidir,PIN_T4,3,B3_N0,3.3-V LVTTL,,
dram_dq[9],Bidir,PIN_T2,3,B3_N0,3.3-V LVTTL,,
dram_dq[10],Bidir,PIN_T3,3,B3_N0,3.3-V LVTTL,,
dram_dq[11],Bidir,PIN_R3,3,B3_N0,3.3-V LVTTL,,
dram_dq[12],Bidir,PIN_R5,3,B3_N0,3.3-V LVTTL,,
dram_dq[13],Bidir,PIN_P3,3,B3_N0,3.3-V LVTTL,,
dram_dq[14],Bidir,PIN_N3,3,B3_N0,3.3-V LVTTL,,
dram_dq[15],Bidir,PIN_K1,2,B2_N0,3.3-V LVTTL,,
dram_dqm[0],Bidir,PIN_R6,3,B3_N0,3.3-V LVTTL,,
dram_dqm[1],Bidir,PIN_T5,3,B3_N0,3.3-V LVTTL,,
dram_cas_n,Output,PIN_L1,2,B2_N0,3.3-V LVTTL,,
dram_ras_n,Output,PIN_L2,2,B2_N0,3.3-V LVTTL,,
dram_we_n,Output,PIN_C2,1,B1_N0,3.3-V LVTTL,,
i2c_sclk,Unknown,PIN_F2,1,B1_N0,3.3-V LVTTL,,
i2c_sdat,Unknown,PIN_F1,1,B1_N0,3.3-V LVTTL,,
g_sensor_cs_n,Unknown,PIN_G5,1,B1_N0,3.3-V LVTTL,,
g_sensor_int,Unknown,PIN_M2,2,B2_N0,3.3-V LVTTL,,
adc_cs_n,Unknown,PIN_A10,7,B7_N0,3.3-V LVTTL,,
adc_saddr,Unknown,PIN_B10,7,B7_N0,3.3-V LVTTL,,
adc_sclk,Unknown,PIN_B14,7,B7_N0,3.3-V LVTTL,,
adc_sdat,Unknown,PIN_A9,7,B7_N0,3.3-V LVTTL,,
gpio_2[0],Unknown,PIN_A14,7,B7_N0,3.3-V LVTTL,,
gpio_2[1],Unknown,PIN_B16,6,B6_N0,3.3-V LVTTL,,
gpio_2[2],Unknown,PIN_C14,7,B7_N0,3.3-V LVTTL,,
gpio_2[3],Unknown,PIN_C16,6,B6_N0,3.3-V LVTTL,,
gpio_2[4],Unknown,PIN_C15,6,B6_N0,3.3-V LVTTL,,
gpio_2[5],Unknown,PIN_D16,6,B6_N0,3.3-V LVTTL,,
gpio_2[6],Unknown,PIN_D15,6,B6_N0,3.3-V LVTTL,,
gpio_2[7],Unknown,PIN_D14,7,B7_N0,3.3-V LVTTL,,
gpio_2[8],Unknown,PIN_F15,6,B6_N0,3.3-V LVTTL,,
gpio_2[9],Unknown,PIN_F16,6,B6_N0,3.3-V LVTTL,,
gpio_2[10],Unknown,PIN_F14,6,B6_N0,3.3-V LVTTL,,
gpio_2[11],Unknown,PIN_G16,6,B6_N0,3.3-V LVTTL,,
gpio_2[12],Unknown,PIN_G15,6,B6_N0,3.3-V LVTTL,,
gpio_2_in[0],Unknown,PIN_E15,6,B6_N0,3.3-V LVTTL,,
gpio_2_in[1],Unknown,PIN_E16,6,B6_N0,3.3-V LVTTL,,
gpio_2_in[2],Unknown,PIN_M16,5,B5_N0,3.3-V LVTTL,,

#pinbelegung:
#1 gnd
#2 gnd
#3 bclk
#4 gnd
#5 daclrc
#6 dacdat
#7 adcdat
#8 adclrc
#9 csb
#10 sdin
#11 -
#12 -
#13 sclk
#14 gnd
#15 mclk
#16 gnd
#
#bottom (from left)
#20 rx_clk xx
#19 rx_dv
#22 crs
#21 rx_er
#24 col
#23 rxd_0
#25 rxd_1
#28 rxd_2
#32 rxd_3
#
#top (from left)
#17 mdc  xx
#18 gnd
#26 mdio
#27 reset_n
#31 tx_en
#34 txd_1
#33 txd_3
#36 tx_clk xx
#35 txd_0
#38 txd_2


#Board 1, GPIO 0
gnd[0]                  ,Input,PIN_A8,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0_IN[0]
gnd[2]                  ,Input,PIN_D3,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[0]
gnd[1]              ,Input,PIN_B8,8,B8_N0,3.3-V LVTTL,,             #GPIO_0_IN[1]
wm8731_bclk_0   ,Output,PIN_C3,8,B8_N0,3.3-V LVTTL,4mA,                 #GPIO_0[1]
wm8731_daclrc_0 ,Output,PIN_A2,8,B8_N0,3.3-V LVTTL,4mA,         #GPIO_0[2]
wm8731_dacdat_0 ,Output,PIN_A3,8,B8_N0,3.3-V LVTTL,4mA,         #GPIO_0[3]
wm8731_adcdat_0 ,Input,PIN_B3,8,B8_N0,3.3-V LVTTL,4mA,                  #GPIO_0[4]
wm8731_adclrc_0 ,Output,PIN_B4,8,B8_N0,3.3-V LVTTL,4mA,         #GPIO_0[5]
wm8731_csb_0    ,Output,PIN_A4,8,B8_N0,3.3-V LVTTL,4mA,         #GPIO_0[6]
wm8731_sdin_0   ,Bidir,PIN_B5,8,B8_N0,3.3-V LVTTL,4mA,                  #GPIO_0[7]
wm8731_sclk_0   ,Output,PIN_A5,8,B8_N0,3.3-V LVTTL,4mA,         #GPIO_0[8]
gnd[3]                  ,Input,PIN_D5,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[9]
wm8731_mclk_0   ,Output,PIN_B6,8,B8_N0,3.3-V LVTTL,4mA,         #GPIO_0[10]
gnd[4]                  ,Input,PIN_A6,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[11]

dp83848_mdc             ,Output,PIN_B7,8,B8_N0,3.3-V LVTTL,,            #GPIO_0[12]
gnd[5]                  ,Input,PIN_D6,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[13]
dp83848_rx_dv   ,Input,PIN_A7,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[14]
dp83848_rx_clk  ,Input,PIN_C6,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[15]
dp83848_rx_er   ,Input,PIN_C8,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[16]
dp83848_rx_crs  ,Input,PIN_E6,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[17]
dp83848_rxd[0]  ,Input,PIN_E7,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[18]
dp83848_rx_col  ,Input,PIN_D8,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[19]
dp83848_rxd[1]  ,Input,PIN_E8,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[20]
dp83848_mdio    ,Bidir,PIN_F8,8,B8_N0,3.3-V LVTTL,,                     #GPIO_0[21]


ftdi_rxd                ,Input,PIN_F9,7,B7_N0,3.3-V LVTTL,4mA,                  #GPIO_1[22]
ftdi_txd                ,Output,PIN_E9,7,B7_N0,3.3-V LVTTL,4mA,                         #GPIO_1[23]

#dp83848_reset_n        ,Output,PIN_F9,7,B7_N0,3.3-V LVTTL,,            #GPIO_0[22]
#dp83848_rxd[2] ,Input,PIN_E9,7,B7_N0,3.3-V LVTTL,,                     #GPIO_0[23]


dp83848_tx_en   ,Output,PIN_C9,7,B7_N0,3.3-V LVTTL,,            #GPIO_0[24]
dp83848_rxd[3]  ,Input,PIN_D9,7,B7_N0,3.3-V LVTTL,,                     #GPIO_0[25]
dp83848_txd[3]  ,Output,PIN_E11,7,B7_N0,3.3-V LVTTL,,           #GPIO_0[26]
dp83848_txd[1]  ,Output,PIN_E10,7,B7_N0,3.3-V LVTTL,,           #GPIO_0[27]
dp83848_txd[0]  ,Output,PIN_C11,7,B7_N0,3.3-V LVTTL,,           #GPIO_0[28]
dp83848_tx_clk  ,Input,PIN_B11,7,B7_N0,3.3-V LVTTL,,            #GPIO_0[29]
dp83848_txd[2]  ,Output,PIN_A12,7,B7_N0,3.3-V LVTTL,,           #GPIO_0[30]
gnd[6]                  ,Input,PIN_D11,7,B7_N0,3.3-V LVTTL,,            #GPIO_0[31]
gnd[7]                  ,Input,PIN_D12,7,B7_N0,3.3-V LVTTL,,            #GPIO_0[32]
gnd[8]                  ,Input,PIN_B12,7,B7_N0,3.3-V LVTTL,,            #GPIO_0[33]


# Board 2, GPIO 1

gnd[9]                  ,Input,PIN_T9,4,B4_N0,3.3-V LVTTL,,                                     #GPIO_1_IN[0]
wm8731_bclk_1   ,Input,PIN_F13,6,B6_N0,3.3-V LVTTL,,                            #GPIO_1[0]
gnd[10]                 ,Output,PIN_R9,4,B4_N0,3.3-V LVTTL,,                            #GPIO_1_IN[1]
gnd[11]                 ,Input,PIN_T15,4,B4_N0,3.3-V LVTTL,,                            #GPIO_1[1]
wm8731_daclrc_1 ,Output,PIN_T14,4,B4_N0,3.3-V LVTTL,,                           #GPIO_1[2]
wm8731_dacdat_1 ,Output,PIN_T13,4,B4_N0,3.3-V LVTTL,,                           #GPIO_1[3]
wm8731_adcdat_1 ,Input,PIN_R13,4,B4_N0,3.3-V LVTTL,,                            #GPIO_1[4]
wm8731_adclrc_1 ,Output,PIN_T12,4,B4_N0,3.3-V LVTTL,,                           #GPIO_1[5]
wm8731_csb_1    ,Output,PIN_R12,4,B4_N0,3.3-V LVTTL,,                           #GPIO_1[6]
wm8731_sdin_1   ,Bidir,PIN_T11,4,B4_N0,3.3-V LVTTL,,                            #GPIO_1[7]
wm8731_sclk_1   ,Output,PIN_T10,4,B4_N0,3.3-V LVTTL,,                           #GPIO_1[8]
gnd[12]                 ,Input,PIN_R11,4,B4_N0,3.3-V LVTTL,,                            #GPIO_1[9]
wm8731_mclk_1   ,Output,PIN_P11,4,B4_N0,3.3-V LVTTL,,                           #GPIO_1[10]
gnd[13]                 ,Input,PIN_R10,4,B4_N0,3.3-V LVTTL,,                            #GPIO_1[11]

sd_sclk                 ,Output,PIN_N12,4,B4_N0,3.3-V LVTTL,,                           #GPIO_1[12]
sd_cdi_n                ,Input,PIN_P9,4,B4_N0,3.3-V LVTTL,,                                     #GPIO_1[13]
sd_dat[1]               ,Bidir,PIN_N9,4,B4_N0,3.3-V LVTTL,,                                     #GPIO_1[14]
sd_dat[0]               ,Bidir,PIN_N11,4,B4_N0,3.3-V LVTTL,,                            #GPIO_1[15]
sd_cmd                  ,Output,PIN_L16,5,B5_N0,3.3-V LVTTL,,                           #GPIO_1[16]
sd_dat[3]               ,Bidir,PIN_K16,5,B5_N0,3.3-V LVTTL,,                            #GPIO_1[17]
sd_dat[2]               ,Bidir,PIN_R16,5,B5_N0,3.3-V LVTTL,,                            #GPIO_1[18]
sd_wp                   ,Input,PIN_L15,5,B5_N0,3.3-V LVTTL,,                            #GPIO_1[19]


gnd[14]                 ,Input,PIN_P15,5,B5_N0,3.3-V LVTTL,,                            #GPIO_1[20]
gnd[15]                 ,Input,PIN_P16,5,B5_N0,3.3-V LVTTL,,                            #GPIO_1[21]
#ftdi_rxd               ,Input,PIN_R14,4,B4_N0,3.3-V LVTTL,4mA,                 #GPIO_1[22]
#ftdi_txd               ,Output,PIN_N16,5,B5_N0,3.3-V LVTTL,4mA,                                #GPIO_1[23]

#unused
gpio_1[24],Unknown,PIN_N15,5,B5_N0,3.3-V LVTTL,,
gpio_1[25],Unknown,PIN_P14,4,B4_N0,3.3-V LVTTL,,
gpio_1[26],Unknown,PIN_L14,5,B5_N0,3.3-V LVTTL,,
gpio_1[27],Unknown,PIN_N14,5,B5_N0,3.3-V LVTTL,,
gpio_1[28],Unknown,PIN_M10,4,B4_N0,3.3-V LVTTL,,
gpio_1[29],Unknown,PIN_L13,5,B5_N0,3.3-V LVTTL,,
gpio_1[30],Unknown,PIN_J16,5,B5_N0,3.3-V LVTTL,,
gpio_1[31],Unknown,PIN_K15,5,B5_N0,3.3-V LVTTL,,
gpio_1[32],Output,PIN_J13,5,B5_N0,3.3-V LVTTL,,
gpio_1[33],Unknown,PIN_J14,5,B5_N0,3.3-V LVTTL,,