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[/] [quark/] [trunk/] [05_HDLConstruction/] [01_OldArchitecture_ReferenceOnly/] [Alu/] [Alu.v] - Rev 10
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//////////////////////////////////////////////// // @file ALU.v // @brief ALU design for Quantum processor // @date 9/6/2014 //////////////////////////////////////////////// `include "Alu.vh" module ModAlu ( input Clock, input Reset, input [0:7] AluInstruction, input [0:7] AluInput1, input [0:7] AluInput2, output reg [0:15] AluResult ); always@(posedge Clock, negedge Reset) begin if (Reset == 1'b0) begin AluResult <= 16'h00; end else begin case (AluInstruction) `Idle: begin AluResult <= AluResult; end `And: begin AluResult <= AluInput2 & AluInput1; end `Or: begin AluResult <= AluInput2 | AluInput1; end `XNOr: begin AluResult <= AluInput2 ^~ AluInput1; end `XOr: begin AluResult <= AluInput2 ^ AluInput1; end `Not: begin AluResult <= {AluInput2, AluInput1}; end `Add: begin AluResult <= AluInput2 + AluInput1; end `Sub: begin AluResult <= AluInput2 - AluInput1; end default: begin AluResult <= AluResult; end endcase end end endmodule //////////////////////////////////////////////// // EOF ////////////////////////////////////////////////