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////////////////////////////////////////////////
// @file  DecodeUnit.v
// @brief Decode Unit for Quantum Processor
// @date  9/28/2014
////////////////////////////////////////////////
 
`include "DecodeUnit.vh"
`include "../ExecuteUnit/ExecuteUnit.vh"
`include "../FetchUnit/FetchUnit.vh"
 
module DecodeUnit (
  input             Clock,
  input             Reset,
  input             RequestDecode,
  input             ExecuteIsBusy,
  input      [0:7]  Opcode,
  input      [0:7]  FetchTemporalReg1,
  input      [0:7]  FetchTemporalReg2,
  input      [0:7]  FetchTemporalReg3,
  output reg [0:15] ExecuteCode,
  output reg        DecodeIsBusy,
  output reg        RequestExecute,
  output reg        MemoryIsCorrupted
  );
 
  reg [0:7] DecodeState;
 
  always@(posedge Clock, negedge Reset) begin
    if (Reset == 1'b0) begin
      DecodeIsBusy <= 1'b1;
      RequestExecute <= 1'b0;
      MemoryIsCorrupted <= 1'b0;
      ExecuteCode <= `idle;
      DecodeState <= `Decode;
    end else begin
      DecodeIsBusy <= 1'b1;
 
      case(DecodeState)
        `Decode: begin
          if (RequestDecode == 1'b1) begin
            DecodeState <= `RequestExecute;
 
            //////////////////////////////////////////////////
            ///// Load Instructions
            //////////////////////////////////////////////////
            if ((Opcode == `ldr) && (FetchTemporalReg1 == `rega)) begin
              ExecuteCode <= `ldr_rega_data;
            end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regb)) begin
              ExecuteCode <= `ldr_regb_data;
            end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regc)) begin
              ExecuteCode <= `ldr_regc_data;
            end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regx)) begin
              ExecuteCode <= `ldr_regx_data;
            end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regy)) begin
              ExecuteCode <= `ldr_regy_data;
            end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regz)) begin
              ExecuteCode <= `ldr_regz_data;
            end else if (Opcode == `ldm) begin
              ExecuteCode <= `ldm_addr_data;
 
            //////////////////////////////////////////////////
            ///// Addition operations
            //////////////////////////////////////////////////
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `addrr_rega_rega;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `addrr_rega_regb;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `addrr_rega_regc;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `addrr_rega_regx;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `addrr_rega_regy;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `addrr_rega_regz;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `addrr_regb_rega;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `addrr_regb_regb;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `addrr_regb_regc;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `addrr_regb_regx;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `addrr_regb_regy;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `addrr_regb_regz;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `addrr_regc_rega;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `addrr_regc_regb;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `addrr_regc_regc;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `addrr_regc_regx;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `addrr_regc_regy;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `addrr_regc_regz;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `addrr_regx_rega;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `addrr_regx_regb;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `addrr_regx_regc;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `addrr_regx_regx;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `addrr_regx_regy;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `addrr_regx_regz;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `addrr_regy_rega;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `addrr_regy_regb;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `addrr_regy_regc;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `addrr_regy_regx;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `addrr_regy_regy;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `addrr_regy_regz;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `addrr_regz_rega;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `addrr_regz_regb;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `addrr_regz_regc;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `addrr_regz_regx;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `addrr_regz_regy;
            end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `addrr_regz_regz;
            end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `rega)) begin
              ExecuteCode <= `addrm_rega_addr;
            end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regb)) begin
              ExecuteCode <= `addrm_regb_addr;
            end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regc)) begin
              ExecuteCode <= `addrm_regc_addr;
            end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regx)) begin
              ExecuteCode <= `addrm_regx_addr;
            end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regy)) begin
              ExecuteCode <= `addrm_regy_addr;
            end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regz)) begin
              ExecuteCode <= `addrm_regz_addr;
            end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `addmr_addr_rega;
            end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `addmr_addr_regb;
            end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `addmr_addr_regc;
            end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `addmr_addr_regx;
            end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `addmr_addr_regy;
            end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `addmr_addr_regz;
            end else if (Opcode == `addmm) begin
              ExecuteCode <= `addmm_addr_addr;
 
            //////////////////////////////////////////////////
            ///// Branch Instructions
            //////////////////////////////////////////////////
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `breqrr_rega_regb;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `breqrr_rega_regc;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `breqrr_rega_regx;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `breqrr_rega_regy;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `breqrr_rega_regz;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `breqrr_regb_rega;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regc)) begin
              ExecuteCode <= `breqrr_regb_regc;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `breqrr_regb_regx;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `breqrr_regb_regy;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `breqrr_regb_regz;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `rega)) begin
              ExecuteCode <= `breqrr_regc_rega;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regb)) begin
              ExecuteCode <= `breqrr_regc_regb;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regx)) begin
              ExecuteCode <= `breqrr_regc_regx;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regy)) begin
              ExecuteCode <= `breqrr_regc_regy;
            end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regz)) begin
              ExecuteCode <= `breqrr_regc_regz;
            end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `rega)) begin
              ExecuteCode <= `breqrm_rega_addr;
            end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regb)) begin
              ExecuteCode <= `breqrm_regb_addr;
            end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regc)) begin
              ExecuteCode <= `breqrm_regc_addr;
            end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regx)) begin
              ExecuteCode <= `breqrm_regx_addr;
            end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regy)) begin
              ExecuteCode <= `breqrm_regy_addr;
            end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regz)) begin
              ExecuteCode <= `breqrm_regz_addr;
            end else if (Opcode == `breqmm) begin
              ExecuteCode <= `breqmm_addr_addr;
 
            //////////////////////////////////////////////////
            ///// Jump Instructions
            //////////////////////////////////////////////////
            end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `rega)) begin
              ExecuteCode <= `jmpr_rega;
            end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regb)) begin
              ExecuteCode <= `jmpr_regb;
            end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regc)) begin
              ExecuteCode <= `jmpr_regc;
            end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regx)) begin
              ExecuteCode <= `jmpr_regx;
            end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regy)) begin
              ExecuteCode <= `jmpr_regy;
            end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regz)) begin
              ExecuteCode <= `jmpr_regz;
            end else if (Opcode == `jmpm) begin
              ExecuteCode <= `jmpm_addr;
            end else begin
              ExecuteCode <= `idle;
              MemoryIsCorrupted <= 1'b0;
              DecodeState <= `Decode;
            end
          end
        end
 
        `RequestExecute: begin
          RequestExecute <= 1'b1;
          DecodeState <= `WaitRequest;
        end
 
        `WaitRequest: begin
          DecodeState <= `WaitExecute;
        end
 
        `WaitExecute: begin
          if (ExecuteIsBusy == 1'b0) begin
            DecodeState <= `ResetDecodeSM;
            RequestExecute <= 1'b0;
            DecodeIsBusy <= 1'b0;
            ExecuteCode <= `idle;
          end
        end
 
        `ResetDecodeSM: begin
          if (RequestDecode == 1'b0) begin
            DecodeState <= `Decode;
          end
        end
      endcase
    end
  end
endmodule
 
////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////