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////////////////////////////////////////////////
// @file  ExecuteUnit.v
// @brief Execute Unit for Quantum Processor
// @date  9/28/2014
////////////////////////////////////////////////
 
`include "ExecuteUnit.vh"
`include "../../Alu/Alu.vh"
 
module ExecuteUnit (
  input             Clock,
  input             Reset,
  input             RequestExecute,
  input      [0:15] AluResult,
  input      [0:15] ExecuteCode,
  input      [0:7]  FetchTemporalReg1,
  input      [0:7]  FetchTemporalReg2,
  input      [0:7]  FetchTemporalReg3,
  output reg [0:7]  REGA,
  output reg [0:7]  REGB,
  output reg [0:7]  REGC,
  output reg [0:7]  REGX,
  output reg [0:7]  REGY,
  output reg [0:7]  REGZ,
  output reg [0:7]  AluInput1,
  output reg [0:7]  AluInput2,
  output reg [0:7]  AluInstruction,
  output reg [0:7]  BusDataOut,
  output reg [0:7]  NewPC,
  output reg        WritePC,
  output reg        ExecuteIsBusy,
  output reg        RequestUnlockPC,
  output reg        WriteEnable
  );
 
  reg [0:7]  InstExecuteState;
 
  always@(posedge Clock, negedge Reset) begin
    if (Reset == 1'b0) begin
      AluInput1 <= 8'h00;
      AluInput2 <= 8'h00;
      AluInstruction <= 8'h00;
      REGA <= 8'h00;
      REGB <= 8'h00;
      REGC <= 8'h00;
      REGX <= 8'h00;
      REGY <= 8'h00;
      REGZ <= 8'h00;
      WritePC <= 1'b0;
      ExecuteIsBusy <= 1'b1;
      RequestUnlockPC <= 1'b0;
      WriteEnable <= 1'b0;
      BusDataOut <= 8'h00;
      InstExecuteState <= 8'h00;
    end else begin
      WritePC <= 1'b0;
 
      if (RequestExecute == 1'b1) begin
        ExecuteIsBusy <= 1'b1;
 
        case (ExecuteCode)
          `idle: begin
            InstExecuteState <= 8'h00;
          end
          `ldr_rega_data: begin
            REGA <= FetchTemporalReg2;
            ExecuteIsBusy <= 1'b0;
          end
          `ldr_regb_data: begin
            REGB <= FetchTemporalReg2;
            ExecuteIsBusy <= 1'b0;
          end
          `ldr_regc_data: begin
            REGC <= FetchTemporalReg2;
            ExecuteIsBusy <= 1'b0;
          end
          `ldr_regx_data: begin
            REGX <= FetchTemporalReg2;
            ExecuteIsBusy <= 1'b0;
          end
          `ldr_regy_data: begin
            REGY <= FetchTemporalReg2;
            ExecuteIsBusy <= 1'b0;
          end
          `ldr_regz_data: begin
            REGZ <= FetchTemporalReg2;
            ExecuteIsBusy <= 1'b0;
          end
          `ldm_addr_data: begin
            case (InstExecuteState)
              8'h00: begin
                BusDataOut <= FetchTemporalReg2;
                InstExecuteState <= 8'h01;
              end
 
              8'h01: begin
                WriteEnable <= 1'b1;
                InstExecuteState <= 8'h02;
              end
 
              8'h02: begin
                WriteEnable <= 1'b0;
                InstExecuteState <= 8'h00;
              end
            endcase
          end
 
          `addrr_rega_regx: begin
            case (InstExecuteState)
              8'h00: begin
                AluInput1 <= REGA;
                AluInput2 <= REGX;
                AluInstruction <= `Add;
                InstExecuteState <= 8'h01;
              end
 
              8'h01: begin
                InstExecuteState <= 8'h02;
              end
 
              8'h02: begin
                AluInstruction <= `Idle;
                REGA <= AluResult[8:15];
                ExecuteIsBusy <= 1'b0;
                InstExecuteState <= 8'h00;
              end
            endcase
          end
 
          `addrr_regb_regx: begin
            case (InstExecuteState)
              8'h00: begin
                AluInput1 <= REGB;
                AluInput2 <= REGX;
                AluInstruction <= `Add;
                InstExecuteState <= 8'h01;
              end
 
              8'h01: begin
                InstExecuteState <= 8'h02;
              end
 
              8'h02: begin
                AluInstruction <= `Idle;
                REGB <= AluResult[8:15];
                ExecuteIsBusy <= 1'b0;
                InstExecuteState <= 8'h00;
              end
            endcase
          end
 
          `addrr_regc_regx: begin
            case (InstExecuteState)
              8'h00: begin
                AluInput1 <= REGC;
                AluInput2 <= REGX;
                AluInstruction <= `Add;
                InstExecuteState <= 8'h01;
              end
 
              8'h01: begin
                InstExecuteState <= 8'h02;
              end
 
              8'h02: begin
                AluInstruction <= `Idle;
                REGC <= AluResult[8:15];
                ExecuteIsBusy <= 1'b0;
                InstExecuteState <= 8'h00;
              end
            endcase
          end
 
          `breqrr_rega_regy: begin
            NewPC <= FetchTemporalReg3;
 
            case (InstExecuteState)
              8'h00: begin
                if (REGA == REGY) begin
                  ExecuteIsBusy <= 1'b0;
                  InstExecuteState <= 8'h01;
                  RequestUnlockPC <= 1'b1;
                end else begin
                  WritePC <= 1'b1;
                  InstExecuteState <= 8'h01;
                end
              end
 
              8'h01: begin
                InstExecuteState <= 8'h02;
              end
 
              8'h02: begin
                RequestUnlockPC <= 1'b0; 
                ExecuteIsBusy <= 1'b0;
                InstExecuteState <= 8'h00;
              end
            endcase
          end
 
          `breqrr_regb_regy: begin
            NewPC <= FetchTemporalReg3;
 
            case (InstExecuteState)
              8'h00: begin
                if (REGB == REGY) begin
                  ExecuteIsBusy <= 1'b0;
                  InstExecuteState <= 8'h01;
                  RequestUnlockPC <= 1'b1;
                end else begin
                  WritePC <= 1'b1;
                  InstExecuteState <= 8'h01;
                end
              end
 
              8'h01: begin
                InstExecuteState <= 8'h02;
              end
 
              8'h02: begin
                RequestUnlockPC <= 1'b0; 
                ExecuteIsBusy <= 1'b0;
                InstExecuteState <= 8'h00;
              end
            endcase
          end
 
          `jmpr_regz: begin
            NewPC <= REGZ;
 
            case (InstExecuteState)
              8'h00: begin // JUMP TO ADDRESS
                WritePC <= 1'b1;
                InstExecuteState <= 8'h01;
              end
 
              8'h01: begin // WAIT FOR MEMORY TO GET VALUE
                InstExecuteState <= 8'h02;
              end
 
              8'h02: begin // RESET STATE MACHINE
                RequestUnlockPC <= 1'b0; 
                ExecuteIsBusy <= 1'b0;
                InstExecuteState <= 8'h00;
              end
            endcase
          end
 
          default: begin
            InstExecuteState <= 8'h00;
          end
        endcase
      end else begin
        InstExecuteState <= 8'h00;
      end
    end
  end
endmodule
 
////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////