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////////////////////////////////////////////////
// @file  FetchUnit.v
// @brief Fetch Control for Quantum Processor
// @date  9/28/2014
////////////////////////////////////////////////
 
`include "FetchUnit.vh"
 
module FetchUnit (
  input            Clock,
  input            Reset,
  input            DecodeIsBusy,
  input            RequestUnlockPC,
  input      [0:7] BusDataIn,
  output reg [0:7] Opcode,
  output reg [0:7] FetchTemporalReg1,
  output reg [0:7] FetchTemporalReg2,
  output reg [0:7] FetchTemporalReg3,
  output reg       RequestDecode,
  output reg       LockPC,
  output reg       PCIsNotLocked,
  output reg       IncrementPC
  );
 
  reg [0:1]  CounterOfBytesToRead;
  reg [0:1]  NumberOfBytesToRead;
  reg [0:7]  FetchState;
 
  always@(posedge Clock, negedge Reset) begin
    if (Reset == 1'b0) begin
      RequestDecode <= 1'b0;
      CounterOfBytesToRead <= 2'b00;
      NumberOfBytesToRead <= 2'b00;
      Opcode <= `nop;
      FetchTemporalReg1 <= 8'h00;
      FetchTemporalReg2 <= 8'h00;
      FetchTemporalReg3 <= 8'h00;
      LockPC <= 1'b0;
      PCIsNotLocked <= 1'b1;
      IncrementPC <= 1'b0;
      FetchState <= `GetOpcode;
    end else begin
      IncrementPC <= 1'b0;
 
      case (FetchState)
        `GetOpcode: begin
          LockPC <= 1'b0;
          PCIsNotLocked <= 1'b1;
          CounterOfBytesToRead <= 2'b00;
          FetchState <= `WaitNumberOfBytesToRead;
          Opcode <= BusDataIn;
 
          case (BusDataIn)
            `ldr: begin
              NumberOfBytesToRead <= 2'b10;
            end
            `ldm: begin
              NumberOfBytesToRead <= 2'b10;
            end
            `addrr: begin
              NumberOfBytesToRead <= 2'b10;
            end
            `addrm: begin
              NumberOfBytesToRead <= 2'b10;
            end
            `addmr: begin
              NumberOfBytesToRead <= 2'b10;
            end
            `addmm: begin
              NumberOfBytesToRead <= 2'b10;
            end
            `breqrr: begin
              LockPC <= 1'b1;
              NumberOfBytesToRead <= 2'b11;
            end
            `breqrm: begin
              LockPC <= 1'b1;
              NumberOfBytesToRead <= 2'b11;
            end
            `breqmm: begin
              LockPC <= 1'b1;
              NumberOfBytesToRead <= 2'b11;
            end
            `jmpr: begin
              LockPC <= 1'b1;
              NumberOfBytesToRead <= 2'b10;
            end
            `jmpm: begin
              LockPC <= 1'b1;
              NumberOfBytesToRead <= 2'b10;
            end
            default: begin
              NumberOfBytesToRead <= 2'b00;
              FetchState <= `GetOpcode;
              Opcode <= `nop;
            end
          endcase
        end
 
        `WaitNumberOfBytesToRead: begin
          FetchState <= `ReadData1;
        end
 
        //////////////////////////////////////////////////
        ///// READ DATA 1
        //////////////////////////////////////////////////
        `ReadData1: begin
          FetchState <= `WaitPCIncrement1;
          CounterOfBytesToRead <= 2'b00;
 
          if (CounterOfBytesToRead < NumberOfBytesToRead) begin
            CounterOfBytesToRead <= CounterOfBytesToRead + 1;
            IncrementPC <= 1'b1;
          end else begin
            FetchState <= `RequestDecode;
          end
        end
 
        `WaitPCIncrement1: begin
          FetchState <= `WaitMemory1;
        end
 
        `WaitMemory1: begin
          FetchState <= `SaveData1;
        end
 
        `SaveData1: begin
          FetchTemporalReg1 <= BusDataIn;
          FetchState <= `ReadData2;
        end
 
        //////////////////////////////////////////////////
        ///// READ DATA 2
        //////////////////////////////////////////////////
        `ReadData2: begin
          FetchState <= `WaitPCIncrement2;
          CounterOfBytesToRead <= 2'b00;
 
          if (CounterOfBytesToRead < NumberOfBytesToRead) begin
            CounterOfBytesToRead <= CounterOfBytesToRead + 1;
            IncrementPC <= 1'b1;
          end else begin
            FetchState <= `RequestDecode;
          end
        end
 
        `WaitPCIncrement2: begin
          FetchState <= `WaitMemory2;
        end
 
        `WaitMemory2: begin
          FetchState <= `SaveData2;
        end
 
        `SaveData2: begin
          FetchTemporalReg2 <= BusDataIn;
          FetchState <= `ReadData3;
        end
 
        //////////////////////////////////////////////////
        ///// READ DATA 3
        //////////////////////////////////////////////////
        `ReadData3: begin
          FetchState <= `WaitPCIncrement3;
          CounterOfBytesToRead <= 2'b00;
 
          if (CounterOfBytesToRead < NumberOfBytesToRead) begin
            CounterOfBytesToRead <= CounterOfBytesToRead + 1;
            IncrementPC <= 1'b1;
          end else begin
            FetchState <= `RequestDecode;
          end
        end
 
        `WaitPCIncrement3: begin
          FetchState <= `WaitMemory3;
        end
 
        `WaitMemory3: begin
          FetchState <= `SaveData3;
        end
 
        `SaveData3: begin
          FetchTemporalReg3 <= BusDataIn;
          FetchState <= `RequestDecode;
        end
 
        //////////////////////////////////////////////////
        ///// Request Decode
        //////////////////////////////////////////////////
        `RequestDecode: begin
          RequestDecode <= 1'b1;
          CounterOfBytesToRead <= 8'h00;
          FetchState <= `WaitDecode;
 
          if (LockPC == 1'b1) begin
            PCIsNotLocked <= 1'b0;
          end
        end
 
        `WaitDecode: begin
          if (DecodeIsBusy == 1'b0) begin
            FetchState <= `IncrementPC;
          end
        end
 
        `IncrementPC: begin
          RequestDecode <= 1'b0;
          IncrementPC <= 1'b1;
          FetchState <= `WaitIncrementPC;
 
          if (RequestUnlockPC == 1'b1) begin
            PCIsNotLocked <= 1'b1;
          end
        end
 
        `WaitIncrementPC: begin
          FetchState <= `ResetFetchSM;
        end
 
        `ResetFetchSM: begin
          FetchState <= `GetOpcode;
        end
      endcase
    end
  end
endmodule
 
////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////