Subversion Repositories quark

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity ROM is port(
  Clock:       in  std_logic;
  Reset:       in  std_logic;
  WriteEnable: in  std_logic;
  DataOut:     out std_logic_vector(7 downto 0);
  DataIn:      in  std_logic_vector(7 downto 0);
  Address:     in  std_logic_vector(7 downto 0)
  );
end ROM;
 
architecture ArchRom of ROM is
  --****************************
  --* Define Opcodes
  --****************************
 
  constant nop:    std_logic_vector(7 downto 0) := x"00";
  constant ldr:    std_logic_vector(7 downto 0) := x"01";
  constant ldm:    std_logic_vector(7 downto 0) := x"02";
  constant addrr:  std_logic_vector(7 downto 0) := x"03";
  constant addrm:  std_logic_vector(7 downto 0) := x"04";
  constant addmr:  std_logic_vector(7 downto 0) := x"05";
  constant addmm:  std_logic_vector(7 downto 0) := x"06";
  constant breqrr: std_logic_vector(7 downto 0) := x"07";
  constant breqrm: std_logic_vector(7 downto 0) := x"08";
  constant breqmm: std_logic_vector(7 downto 0) := x"09";
  constant jmpr:   std_logic_vector(7 downto 0) := x"0A";
  constant jmpm:   std_logic_vector(7 downto 0) := x"0B";
 
  --****************************
  --* Define Registers
  --****************************
 
  constant rega: std_logic_vector(7 downto 0) := x"00";
  constant regb: std_logic_vector(7 downto 0) := x"01";
  constant regc: std_logic_vector(7 downto 0) := x"02";
  constant regx: std_logic_vector(7 downto 0) := x"03";
  constant regy: std_logic_vector(7 downto 0) := x"04";
  constant regz: std_logic_vector(7 downto 0) := x"05";
 
  --****************************
  --* Define Asm Labels
  --****************************
 
  constant LoopLabel: std_logic_vector(7 downto 0) := x"12";
 
  type ROMA is array(0 to 255) of std_logic_vector(7 downto 0);
  signal ROM1: ROMA:=(
    --##################################
    --## PROGRAM 1
    --##################################
 
    ldr, rega, x"00",
    ldr, regb, x"00",
    ldr, regc, x"00",
    ldr, regx, x"01",
    ldr, regy, x"ff",
    ldr, regz, LoopLabel,
 
--LoopLabel:
    addrr,  rega, regx,
    breqrr, rega, regy, LoopLabel,
    ldr,    rega, x"00",
    addrr,  regb, regx,
    breqrr, regb, regy, LoopLabel,
    ldr,    regb, x"00",
    addrr,  regc, regx,
    jmpr,   regz,
 
 
    --adda,  x"01",
    --brnea, x"FF", x"00",
    --lda,   x"00", 
    --addb,  x"01",
    --brneb, x"FF", x"00",
    --addc,  x"01", 
    --ldgpc,
    --ldb,   x"00", 
    --jmp,   x"00",
 
    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00"), 
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    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00"), 
    (x"00")
  );
  attribute ramstyle : string;
  --attribute ramstyle of ROM1 : signal is "M512";
begin
  process(Clock, Reset) begin
    if (Reset = '0') then
      DataOut <= x"00";
    elsif rising_edge(Clock) then
      if (WriteEnable = '1') then
        ROM1 (conv_integer(Address)) <= DataIn;
      else
        DataOut <= ROM1(conv_integer(Address));
      end if;
    end if;
  end process;
end ArchRom;