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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity contador is port(
   clk, rst: in std_logic;
   DECO: out std_logic_vector(6 downto 0);
	AP: out std_logic;
	barrido: out std_logic_vector(2 downto 0));
end contador;
 
architecture cont of contador is
   type states is (state0, state1, state2);
	signal state: states;
	signal cnt1, cnt2: std_logic_vector(31 downto 0);
	signal contU, contD, contC: std_logic_vector(3 downto 0);
   signal temp1, temp2: std_logic;
	signal p1, p2, p3: std_logic;
	signal MUX: std_logic_vector(3 downto 0);
	signal barr: std_logic_vector(2 downto 0);
begin
 
divisor1: process(clk,rst)
   begin
      if (rst='1') then
         temp1 <= '0';
         cnt1 <= conv_std_logic_vector(0,32);
      elsif(clk'event and clk='1') then
         if (cnt1=conv_std_logic_vector(25000000,32)) then
            temp1 <= not temp1;
            cnt1 <= conv_std_logic_vector(0,32);
         else
            cnt1 <= cnt1 + 1;
         end if;
      end if;
   end process;
 
divisor2: process(clk,rst)
   begin
      if (rst='1') then
         temp2 <= '0';
         cnt2 <= conv_std_logic_vector(0,32);
      elsif(clk'event and clk='1') then
         if (cnt2=conv_std_logic_vector(125000,32)) then
            temp2 <= not temp2;
            cnt2 <= conv_std_logic_vector(0,32);
         else
            cnt2 <= cnt2 + 1;
         end if;
      end if;
   end process;
 
contador1: process(temp1,rst)
   begin
	   if (rst='1') then
		   contU <= conv_std_logic_vector(0,4);
		elsif(temp1'event and temp1='1') then
		   if contU < 9 then
			   contU <= contU + 1;
				p1 <= '0';
			elsif contU = 9 then
			   contU <= conv_std_logic_vector(0,4);
				p1 <= '1';
			end if;
		end if;
	end process;
 
contador2: process(p1,rst)
   begin
	   if (rst='1') then
		   contD <= conv_std_logic_vector(0,4);
		elsif(p1'event and p1='1') then
		   if contD < 9 then
			   contD <= contD + 1;
				p2 <= '0';
			elsif contD = 9 then
			   contD <= conv_std_logic_vector(0,4);
				p2 <= '1';
			end if;
		end if;
	end process;
 
contador3: process(p2,rst)
   begin
	   if (rst='1') then
		   contC <= conv_std_logic_vector(0,4);
		elsif(p2'event and p2='1') then
		   if contC < 9 then
			   contC <= contC + 1;
				p3 <= '0';
			elsif contC = 9 then
			   contC <= conv_std_logic_vector(0,4);
				p3 <= '1';
			end if;
		end if;
	end process;
 
BD: process(temp2,rst)
   begin
	   if (rst='1') then
		   barrido <= conv_std_logic_vector(0,3);
			barr <= conv_std_logic_vector(0,3);
			state <= state0;
		elsif(temp2'event and temp2='1') then
		   case state is
			   when state0 =>
				   barrido <= "110";
					barr <= "110";
				   state <= state1;
				when state1 =>
				   barrido <= "101";
					barr <= "101";
					state <= state2;
				when state2 =>
				   barrido <= "011";
					barr <= "011";
					state <= state0;
			end case;
		end if;
	end process;
 
--MUX
 
   MUX <= contU when barr = "110" else
	       contD when barr = "101" else
			 contC when barr = "011";
 
--DECO
 
	DECO <= "1000000" when mux = "0000" else
	        "1111001" when mux = "0001" else
			  "0100100" when mux = "0010" else
			  "0110000" when mux = "0011" else
			  "0011001" when mux = "0100" else
			  "0010010" when mux = "0101" else
			  "0000010" when mux = "0110" else
			  "1111000" when mux = "0111" else
			  "0000000" when mux = "1000" else
			  "0011000" when mux = "1001" else
			  "0000110";
 
--AP
   AP <= '1';
end cont;