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https://opencores.org/ocsvn/radiohdl/radiohdl/trunk
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[/] [radiohdl/] [trunk/] [config/] [hdl_buildset_unb2c.cfg] - Rev 7
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# Uniboard 2c configuration
buildset_name = unb2c
technology_names = ip_arria10_e1sg
family_names = arria10
block_design_names = qsys
synth_tool_name = quartus
synth_tool_version = 18.0
sim_tool_name = modelsim
sim_tool_version = 10.4
lib_root_dirs = ${RADIOHDL_WORK}/libraries ${RADIOHDL_WORK}/applications ${RADIOHDL_WORK}/boards
[quartus]
quartus_dir = ${ALTERA_DIR}/<synth_tool_version>
[modelsim]
modelsim_dir = ${MENTOR_DIR}/<sim_tool_version>/questasim
modelsim_platform = linux_x86_64
modelsim_search_libraries =
# arria10 only
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
# both stratixiv and arria10
#altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
#altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip twentynm twentynm_hssi twentynm_hip
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