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[/] [reed_solomon_coder/] [trunk/] [division.v] - Rev 6
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`timescale 1ns / 1ps module division(A,B,Res); input [31:0] A; input [31:0] B; output [31:0] Res; reg [31:0] Res = 0; reg [31:0] a1,b1; reg [32:0] p1; integer i; always@ (A or B) begin a1 = A; b1 = B; p1= 0; for(i=0;i < 32;i=i+1) begin p1 = {p1[30:0],a1[31]}; a1[31:1] = a1[30:0]; p1 = p1-b1; if(p1[31] == 1) begin a1[0] = 0; p1 = p1 + b1; end else a1[0] = 1; end Res = a1; end endmodule
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