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/** @page irqctrl_page Interrupt Controller
@section irqmp_overview IRQ assignments
IRQ pins configuration is the part of generic constants defined in file
<i>ambalib/types_amba4.vhd</i>. Number of interrupts and its indexes can
changed in future releases.
| Pin | Name | Description
|:----:|:----------|:------------------------------------------------------------|
| 0 | Unused | <b>Zero</b> Interrupt pin is unsued and connected to Ground.
| 1 | UART1 | <b>Uart 1 IRQ</b>. UART device used this line to signal CPU via Interrupt Controller that new data is available or device ready to accept new Rx data.
| 2 | ETHMAC | <b>Ethernet IRQ</b>.
| 3 | GPTIMERS | <b>General Purpose Timers IRQ</b>.
| 4 | MISS_ACCESS | <b>Memory Miss Access IRQ</b>. This interrupt is generated by AXI Controller in a case of access to unmapped memory region.
| 5 | GNSSENGINE | <b>Gnss Engine IRQ</b>. Device Specific 1 msec interrupt that schedules critical Navigation Task.
@section irqmp_regs IRQ Controller registers mapping
IRQ Controller acts like a slave AMBA AXI4 device that is directly mapped
into physical memory. Default address location for our implementation
is defined by 0x80002000. Memory size is 4 KB.
@par Interrupts Mask register (0x000).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32-N | RW | h'0 | reserved | 31:N | Reserved
| N | RW | all 1 | mask | N-1:0 | <b>IRQ mask</b>. 1 equals interrupt disabled; 0 is enabled.
@par Pending Interrupts register (0x004).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32-N | RO | h'0 | reserved | 31:N | Reserved
| N | RO | 0 | pending | N-1:0 | <b>Pending Bits</b>. 1 signals rised interrupt. This bit is cleared by writing 1 into the register 'Clear IRQ' or writing 1 into 'Lock Register'.
@par Clear Interrupt Mask register (0x008).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32-N | WO | h'0 | reserved | 31:N | Reserved
| N | WO | 0 | clear_bit| N-1:0 | <b>Clear IRQ line</b>. Clear Pending interrupt register bits that are marked with 1s.
@par Raise Interrupt Mask register (0x00C).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32-N | WO | h'0 | reserved | 31:N | Reserved
| N | WO | 0 | raise_irq| N-1:0 | <b>Rise specified IRQ line manually</b>. This register can be used for test and debugging either as for 'system calls'.
@par ISR table address (low word) (0x010).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32 | WR | 0 | isr_table| 31:0 | <b>Interrupts table address LSB</b>. This register stores address where located ISR table. This value must be intialized be Software.
@par ISR table address (high word) (0x014).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32 | WR | 0 | isr_table| 31:0 | <b>Interrupts table address MSB</b>. This register stores address where located ISR table. This value must be intialized be Software.
@par ISR cause code (low word) (0x018).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32 | WR | 0 | dbg_cause| 31:0 | <b>Cause of te Interrupt LSB</b>. This register stores the latest cause of the interrupt. This value is optional and updates by ROM ISR handler in current implementation.
@par ISR cause code (high word) (0x01C).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32 | WR | 0 | dbg_cause| 31:0 | <b>Cause of the Interrupt MSB</b>. This register stores the latest cause of the interrupt. This value is optional and updates by ROM ISR handler in current implementation.
@par Instruction Pointer before trap (low word) (0x020).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32 | WR | 0 | dbg_epc | 31:0 | <b>npc[31:0] register value before trap </b>. This register stores copy of xEPC value. This value is optional and updates by ROM ISR handler in current implementation.
@par Instruction Pointer before trap (high word) (0x024).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32 | WR | 0 | dbg_epc | 31:0 | <b>npc[63:32] register value before trap</b>. This register stores copy of xEPC value. This value is optional and updates by ROM ISR handler in current implementation.
@par Lock interrupt register (0x028).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 31 | WR | 31h'0 | reserved | 31:1 | Reserved
| 1 | WR | 1b' | lock | 0 | <b>Lock interrupts</b>. Disabled all interrupts when this bit is 1. All new interrupt request marked as postponed and will be raised when 'lock' signal will be cleared.
@par Lock interrupt register (0x02C).
| Bits |Type| Reset |Field Name| Bits | Description
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
| 32 | WR | 0 | irq_idx | 31:0 | <b>Interrupt Index</b>. This register stores current interrupt index while in ISR handler. This value is optional and updates by ROM ISR handler in current implementation.
*/