Subversion Repositories riscv_vhdl

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%===== C O N T E N T S =====
 
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\begin{titlepage}
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{\Large Synthesizable System-on-Chip}\\
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{\Large with 64-bits RISC-V processor core}\\
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{\Large Technical Reference Manual}\\
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{\scshape Generated:    \today}\\
{\scshape Author: Sergey Khabarov}
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  & Name & Position & Signature &  Date \\
\hline
Prepared by & Sergey Khabarov & Technical Lead &  & \\
\hline
Reviewed by & Denis Nefedov &  &  & \\
\hline
Approved by &  &  &  & \\
\hline
Approved by &  &  &  & \\
\hline
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